Add some simplifications for MULH[SU]. This allows us to compile this:

long %bar(long %X) {
  %Y = mul long %X, 4294967297
  ret long %Y
}

to this:

l1_bar:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, %EAX
        add %EDX, DWORD PTR [%ESP + 8]
        ret

instead of:

l1_bar:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EDX, 1
        mov %EAX, %ECX
        mul %EDX
        add %EDX, %ECX
        add %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %ECX
        ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22044 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c3889dd7ff81f6e15c8495abba46d52c5a1df3c1..75e07ca7620c0ed37f0ee40fbd3f7da18260f06d 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -843,6 +843,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
   case ISD::XOR:
   case ISD::UDIV:
   case ISD::UREM:
+  case ISD::MULHU:
+  case ISD::MULHS:
     assert(MVT::isInteger(VT) && "This operator does not apply to FP types!");
     // fall through
   case ISD::ADD:
@@ -941,6 +943,16 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
       }
       break;
 
+    case ISD::MULHU:
+    case ISD::MULHS:
+      if (!C2) return N2;         // mul X, 0 -> 0
+
+      if (C2 == 1)                // 0X*01 -> 0X  hi(0X) == 0
+        return getConstant(0, VT);
+
+      // Many others could be handled here, including -1, powers of 2, etc.
+      break;
+
     case ISD::UDIV:
       // FIXME: Move this to the DAG combiner when it exists.
       if ((C2 & C2-1) == 0 && C2) {