rk3288: clk: support clk_vop set 594M.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index a83dac9bcfea5fe5a2b8c63a32115bfe0dc43c5f..ec1620797706cc98d4c77fc37b985c1bf5cdf978 100755 (executable)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -502,7 +502,7 @@
                        <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
                        <&usbphy_480m &otgphy2_480m>;
                rockchip,clocks-init-rate =
-                       <&clk_core 792000000>,  <&clk_gpll 297000000>,
+                       <&clk_core 792000000>,  <&clk_gpll 594000000>,
                        /*<&clk_cpll 47000000>,*/       <&clk_npll 1250000000>,
                        <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
                        <&hclk_bus 150000000>,  <&pclk_bus 75000000>,

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index b4d143c174bc4071d0aef2acdd5a5852ac537661..a10c62ae924cbd42c90a40e83635274af0421060 100644 (file)
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -605,13 +605,14 @@ static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long
 {
        struct clk *gpll = clk_get(NULL, "clk_gpll");
        struct clk *cpll = clk_get(NULL, "clk_cpll");
-       unsigned long best, div, prate;
+       unsigned long best, div, prate, gpll_rate;
 
+       gpll_rate = __clk_get_rate(gpll);
 
-       if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
+       if ((rate <= (297*MHZ)) && (gpll_rate%rate == 0)) {
                *best_parent_p = gpll;
                best = rate;
-               *best_parent_rate = 297*MHZ;
+               *best_parent_rate = gpll_rate;
        } else {
                *best_parent_p = cpll;
                div = RK3288_LIMIT_PLL_VIO0/rate;
@@ -636,17 +637,19 @@ static int clk_3288_dclk_lcdc0_set_rate(struct clk_hw *hw, unsigned long rate,
        struct clk* hclk_vio = clk_get(NULL, "hclk_vio");
        struct clk *aclk_vio1;
        struct clk* parent;
+       struct clk *gpll = clk_get(NULL, "clk_gpll");
+       struct clk *cpll = clk_get(NULL, "clk_cpll");
 
        clk_divider_ops.set_rate(hw, rate, parent_rate);
 
        /* set aclk_vio */
-       if(parent_rate  == 297*MHZ)
-               parent = clk_get(NULL, "clk_gpll");
-       else
-               parent = clk_get(NULL, "clk_cpll");
-
-       clk_set_parent(aclk_vio0, parent);
-       clk_set_rate(aclk_vio0, __clk_get_rate(parent));
+       if (parent_rate == __clk_get_rate(gpll)) {
+               clk_set_parent(aclk_vio0, gpll);
+               clk_set_rate(aclk_vio0, 300*MHZ);
+       } else {
+               clk_set_parent(aclk_vio0, cpll);
+               clk_set_rate(aclk_vio0, __clk_get_rate(cpll));
+       }
        clk_set_rate(hclk_vio, 100*MHZ);
 
        /* make aclk_isp and hclk_isp share a same pll in rk3288_eco */
@@ -674,13 +677,14 @@ static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long
 {
        struct clk *gpll = clk_get(NULL, "clk_gpll");
        struct clk *cpll = clk_get(NULL, "clk_cpll");
-       unsigned long best, div, prate;
+       unsigned long best, div, prate, gpll_rate;
 
+       gpll_rate = __clk_get_rate(gpll);
 
-       if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
+       if ((rate <= (297*MHZ)) && ((gpll_rate)%rate == 0)) {
                *best_parent_p = gpll;
                best = rate;
-               *best_parent_rate = 297*MHZ;
+               *best_parent_rate = gpll_rate;
        } else {
                *best_parent_p = cpll;
                div = RK3288_LIMIT_PLL_VIO1/rate;
@@ -703,14 +707,19 @@ static int clk_3288_dclk_lcdc1_set_rate(struct clk_hw *hw, unsigned long rate,
 {
        struct clk* aclk_vio1 = clk_get(NULL, "aclk_vio1");
        struct clk* parent;
+       struct clk *gpll = clk_get(NULL, "clk_gpll");
+       struct clk *cpll = clk_get(NULL, "clk_cpll");
 
        clk_divider_ops.set_rate(hw, rate, parent_rate);
 
        /* set aclk_vio */
-       if(parent_rate  == 297*MHZ)
-               parent = clk_get(NULL, "clk_gpll");
-       else
-               parent = clk_get(NULL, "clk_cpll");
+       if (parent_rate == __clk_get_rate(gpll)) {
+               clk_set_parent(aclk_vio1, gpll);
+               clk_set_rate(aclk_vio1, 300*MHZ);
+       } else {
+               clk_set_parent(aclk_vio1, cpll);
+               clk_set_rate(aclk_vio1, __clk_get_rate(cpll));
+       }
 
        if (rockchip_get_cpu_version() == 0) {
                clk_set_parent(aclk_vio1, parent);

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
old mode 100755 (executable)
new mode 100644 (file)
index 325eb2c..ebbd25c
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -898,7 +898,7 @@ static int clk_pll_set_rate_3188plus(struct clk_hw *hw, unsigned long rate,
                clk_set++;
        }
 
-       if (cpu_is_rk3288() && (rate == 297*MHZ)) {
+       if (cpu_is_rk3288() && ((rate == 297*MHZ) || (rate == 594*MHZ))) {
                if((strncmp(__clk_get_name(hw->clk), "clk_gpll",
                        strlen("clk_gpll")) == 0)) {