// experimentally as a minimum needed to prevent unprofitable
// vectorization for the paq8p benchmark. It may need to be
// raised further if other unprofitable cases remain.
- unsigned LHSPenalty = 12;
+ unsigned LHSPenalty = 2;
+ if (ISD == ISD::INSERT_VECTOR_ELT)
+ LHSPenalty += 7;
// Vector element insert/extract with Altivec is very expensive,
// because they require store and reload with the attendant
unsigned Cost =
TargetTransformInfo::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
- // FIXME: Update this for VSX loads/stores that support unaligned access.
+ // VSX loads/stores support unaligned access.
+ if (ST->hasVSX()) {
+ if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
+ return Cost;
+ }
+
+ bool UnalignedAltivec =
+ Src->isVectorTy() &&
+ Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() &&
+ LT.second.getSizeInBits() == 128 &&
+ Opcode == Instruction::Load;
// PPC in general does not support unaligned loads and stores. They'll need
// to be decomposed based on the alignment factor.
unsigned SrcBytes = LT.second.getStoreSize();
- if (SrcBytes && Alignment && Alignment < SrcBytes)
+ if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) {
Cost += LT.first*(SrcBytes/Alignment-1);
+ // For a vector type, there is also scalarization overhead (only for
+ // stores, loads are expanded using the vector-load + permutation sequence,
+ // which is much less expensive).
+ if (Src->isVectorTy() && Opcode == Instruction::Store)
+ for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
+ Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
+ }
+
return Cost;
}
target triple = "powerpc64-unknown-linux-gnu"
define i32 @insert(i32 %arg) {
- ; CHECK: cost of 13 {{.*}} insertelement
+ ; CHECK: cost of 10 {{.*}} insertelement
%x = insertelement <4 x i32> undef, i32 %arg, i32 0
ret i32 undef
}
define i32 @extract(<4 x i32> %arg) {
- ; CHECK: cost of 13 {{.*}} extractelement
+ ; CHECK: cost of 3 {{.*}} extractelement
%x = extractelement <4 x i32> %arg, i32 0
ret i32 %x
}
; FIXME: There actually are sub-vector Altivec loads, and so we could handle
; this with a small expense, but we don't currently.
- ; CHECK: cost of 60 {{.*}} load
+ ; CHECK: cost of 48 {{.*}} load
load <4 x i16>* undef, align 2
+ ; CHECK: cost of 1 {{.*}} load
+ load <4 x i32>* undef, align 4
+
ret i32 undef
}