Rename

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31364 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index ead631578cadf3070424b76828df342c9598f631..48634178c27c07937c9909b32258bc879bf98f5b 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -240,9 +240,9 @@ public:
     return -1;
   }
 
-  /// getTiedToSrcOperand - Returns the operand that is tied to the specified
+  /// findTiedToSrcOperand - Returns the operand that is tied to the specified
   /// dest operand. Returns -1 if there isn't one.
-  int getTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
+  int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
 
   /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
   /// instruction if it has one.  This is used by codegen passes that update

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 0a9112496184fb5935ff88fa8bedcf462a86353f..088be47e14d85a4c70567d0b9cbdd83d960c21b9 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -200,7 +200,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         if (physReg == 0) {
           if (op.isDef()) {
             int TiedOp = TM->getInstrInfo()
-              ->getTiedToSrcOperand(MI->getOpcode(), i);
+              ->findTiedToSrcOperand(MI->getOpcode(), i);
             if (TiedOp == -1) {
               physReg = getFreeReg(virtualReg);
             } else {

diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 911c5c6b79232d97de7b36f9b2b0c65c70cc78ee..522590a1a9ec75ed6a10eff35afd08707c4353c2 100644 (file)
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -821,7 +821,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
         // If this def is part of a two-address operand, make sure to execute
         // the store from the correct physical register.
         unsigned PhysReg;
-        int TiedOp = TII->getTiedToSrcOperand(MI.getOpcode(), i);
+        int TiedOp = TII->findTiedToSrcOperand(MI.getOpcode(), i);
         if (TiedOp != -1)
           PhysReg = MI.getOperand(TiedOp).getReg();
         else

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 81759098ed85f6cb6da040ba78f86e1249e97d04..d28f1e7c50531ac8985a6bd889e4e598281053ad 100644 (file)
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -38,8 +38,10 @@ TargetInstrInfo::~TargetInstrInfo() {
   TargetInstrDescriptors = NULL; // reset global variable
 }
 
+/// findTiedToSrcOperand - Returns the operand that is tied to the specified
+/// dest operand. Returns -1 if there isn't one.
 int
-TargetInstrInfo::getTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const {
+TargetInstrInfo::findTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const {
   for (unsigned i = 0, e = getNumOperands(Opc); i != e; ++i) {
     if (i == OpNum)
       continue;