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Fix typo in PerformAddCombine that caused any vector type to be checked for horizonta...
author
Craig Topper
<craig.topper@gmail.com>
Fri, 13 Jan 2012 05:04:25 +0000
(
05:04
+0000)
committer
Craig Topper
<craig.topper@gmail.com>
Fri, 13 Jan 2012 05:04:25 +0000
(
05:04
+0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148096
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
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diff --git
a/lib/Target/X86/X86ISelLowering.cpp
b/lib/Target/X86/X86ISelLowering.cpp
index 6a5e6f5f240e260a895068970b49cc0c48a586ae..a6f22fafeeaf8c9ae863d0db26c016796eb4be3b 100644
(file)
--- a/
lib/Target/X86/X86ISelLowering.cpp
+++ b/
lib/Target/X86/X86ISelLowering.cpp
@@
-14575,7
+14575,7
@@
static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
// Try to synthesize horizontal adds from adds of shuffles.
if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
- (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) &&
+ (Subtarget->hasAVX2() && (VT == MVT::v16i16 ||
VT ==
MVT::v8i32))) &&
isHorizontalBinOp(Op0, Op1, true))
return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);