Rename PrintableName to Name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index dbf77475aad64fc630d9d8178d3277a951690130..e13ebdab3b5aa535604165eb0a5d66fe872d4d25 100644 (file)
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -49,7 +49,7 @@ class Type;
 ///
 struct TargetRegisterDesc {
   const char     *AsmName;      // Assembly language name for the register
-  const char     *PrintableName;// Printable name for the reg (for debugging)
+  const char     *Name;         // Printable name for the reg (for debugging)
   const unsigned *AliasSet;     // Register Alias Set, described above
   const unsigned *SubRegs;      // Sub-register set, described above
   const unsigned *ImmSubRegs;   // Immediate sub-register set, described above
@@ -376,16 +376,16 @@ public:
     return get(RegNo).SuperRegs;
   }
 
-  /// getAsmName - Return the symbolic target specific name for the
+  /// getAsmName - Return the symbolic target-specific name for the
   /// specified physical register.
   const char *getAsmName(unsigned RegNo) const {
     return get(RegNo).AsmName;
   }
 
-  /// getPrintableName - Return the human-readable symbolic target specific name
-  /// for the specified physical register.
-  const char *getPrintableName(unsigned RegNo) const {
-    return get(RegNo).PrintableName;
+  /// getName - Return the human-readable symbolic target-specific name for the
+  /// specified physical register.
+  const char *getName(unsigned RegNo) const {
+    return get(RegNo).Name;
   }
 
   /// getNumRegs - Return the number of registers this target has (useful for

diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp
index cc932451ace83e590aa0666dd812ca1cd2516a22..48c25a14a3506a687fd0bc88b31758599c1bb50b 100644 (file)
--- a/lib/CodeGen/LiveInterval.cpp
+++ b/lib/CodeGen/LiveInterval.cpp
@@ -665,7 +665,7 @@ void LiveRange::dump() const {
 void LiveInterval::print(std::ostream &OS,
                          const TargetRegisterInfo *TRI) const {
   if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
-    OS << TRI->getPrintableName(reg);
+    OS << TRI->getName(reg);
   else
     OS << "%reg" << reg;
 

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 8ffffe1601877224e61f64c6a2787a50e9d3a1b3..716c3701102f1b45c358e4328b2c31baa1570786 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -189,7 +189,7 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li,
 
 void LiveIntervals::printRegName(unsigned reg) const {
   if (TargetRegisterInfo::isPhysicalRegister(reg))
-    cerr << tri_->getPrintableName(reg);
+    cerr << tri_->getName(reg);
   else
     cerr << "%reg" << reg;
 }

diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index 5ca18d086acc2aa16f4a27c0fb1486d97e598a56..dc6a618d34c782fffa5e7d1781a908ab7e60ea5d 100644 (file)
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -146,7 +146,7 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
                              const TargetRegisterInfo *TRI = 0) {
   if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
     if (TRI)
-      os << " %" << TRI->get(RegNo).PrintableName;
+      os << " %" << TRI->get(RegNo).Name;
     else
       os << " %mreg(" << RegNo << ")";
   } else

diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index 1e0171a39f650b9171feda3c5c4285e1bc7e9391..30896172883e431b5d45ed6305b243900a359d00 100644 (file)
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -214,7 +214,7 @@ void MachineFunction::print(std::ostream &OS) const {
     for (MachineRegisterInfo::livein_iterator
          I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
       if (TRI)
-        OS << " " << TRI->getPrintableName(I->first);
+        OS << " " << TRI->getName(I->first);
       else
         OS << " Reg #" << I->first;
       
@@ -228,7 +228,7 @@ void MachineFunction::print(std::ostream &OS) const {
     for (MachineRegisterInfo::liveout_iterator
          I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
       if (TRI)
-        OS << " " << TRI->getPrintableName(*I);
+        OS << " " << TRI->getName(*I);
       else
         OS << " Reg #" << *I;
     OS << "\n";

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index e9262652c433cba46c624c4ffa827f2aa6e394c2..52c42b3f1165ad6d78897a51ce22fd4e13806efe 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -174,7 +174,7 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
               TM = &MF->getTarget();
       
       if (TM)
-        OS << "%" << TM->getRegisterInfo()->get(getReg()).PrintableName;
+        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
       else
         OS << "%mreg" << getReg();
     }

diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index dcca8856d284eef375ba488663ae07a0bdc6c3c9..89ab93df0a63b133b905419145069041e38ee850 100644 (file)
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -251,7 +251,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
         const TargetRegisterInfo *TRI = TM->getRegisterInfo();
         for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
              *ImpUses; ++ImpUses)
-          DOUT << "      -> " << TRI->getPrintableName(*ImpUses) << "\n";
+          DOUT << "      -> " << TRI->getName(*ImpUses) << "\n";
       }
 
       if (I.getDesc().getImplicitDefs()) {
@@ -260,7 +260,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
         const TargetRegisterInfo *TRI = TM->getRegisterInfo();
         for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
              *ImpDefs; ++ImpDefs)
-          DOUT << "      -> " << TRI->getPrintableName(*ImpDefs) << "\n";
+          DOUT << "      -> " << TRI->getName(*ImpDefs) << "\n";
       }
 
         //if (TII->hasUnmodelledSideEffects(&I))

diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index efd86bf8194cb29d280bfd89dd61a7f7577df70e..0c6c25439a7794c461884db329e8ac6fceac6219 100644 (file)
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -311,7 +311,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
   assert(VirtReg && "Spilling a physical register is illegal!"
          " Must not have appropriate kill for the register or use exists beyond"
          " the intended one.");
-  DOUT << "  Spilling register " << RegInfo->getPrintableName(PhysReg)
+  DOUT << "  Spilling register " << RegInfo->getName(PhysReg)
        << " containing %reg" << VirtReg;
   
   const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@@ -535,7 +535,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
   markVirtRegModified(VirtReg, false);
 
   DOUT << "  Reloading %reg" << VirtReg << " into "
-       << RegInfo->getPrintableName(PhysReg) << "\n";
+       << RegInfo->getName(PhysReg) << "\n";
 
   // Add move instruction(s)
   TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
@@ -646,7 +646,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
           DOUT << "  Regs have values: ";
           for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
             if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
-               DOUT << "[" << RegInfo->getPrintableName(i)
+               DOUT << "[" << RegInfo->getName(i)
                     << ",%reg" << PhysRegsUsed[i] << "] ";
           DOUT << "\n");
 
@@ -700,14 +700,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT << "  Last use of " << RegInfo->getPrintableName(PhysReg)
+        DOUT << "  Last use of " << RegInfo->getName(PhysReg)
              << "[%reg" << VirtReg <<"], removing it from live set\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
             DOUT  << "  Last use of "
-                  << RegInfo->getPrintableName(*AliasSet)
+                  << RegInfo->getName(*AliasSet)
                   << "[%reg" << VirtReg <<"], removing it from live set\n";
             removePhysReg(*AliasSet);
           }
@@ -806,14 +806,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT  << "  Register " << RegInfo->getPrintableName(PhysReg)
+        DOUT  << "  Register " << RegInfo->getName(PhysReg)
               << " [%reg" << VirtReg
               << "] is never used, removing it frame live list\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
-            DOUT  << "  Register " << RegInfo->getPrintableName(*AliasSet)
+            DOUT  << "  Register " << RegInfo->getName(*AliasSet)
                   << " [%reg" << *AliasSet
                   << "] is never used, removing it frame live list\n";
             removePhysReg(*AliasSet);

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index aa042c75c1fcf624ac8cfdacfd7b49de83f343e4..dd3ea7d0a23aa4048e7b2d52ceb124952cbc60ec 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -164,7 +164,7 @@ namespace {
         if (TargetRegisterInfo::isVirtualRegister(reg)) {
           reg = vrm_->getPhys(reg);
         }
-        DOUT << tri_->getPrintableName(reg) << '\n';
+        DOUT << tri_->getName(reg) << '\n';
       }
     }
   };
@@ -239,7 +239,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
 
   // Try to coalesce.
   if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
-    DOUT << "Coalescing: " << cur << " -> " << tri_->getPrintableName(SrcReg)
+    DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg)
          << '\n';
     vrm_->clearVirt(cur.reg);
     vrm_->assignVirt2Phys(cur.reg, SrcReg);
@@ -628,7 +628,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   // the free physical register and add this interval to the active
   // list.
   if (physReg) {
-    DOUT <<  tri_->getPrintableName(physReg) << '\n';
+    DOUT <<  tri_->getName(physReg) << '\n';
     vrm_->assignVirt2Phys(cur->reg, physReg);
     prt_->addRegUse(physReg);
     active_.push_back(std::make_pair(cur, cur->begin()));
@@ -690,7 +690,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   }
   
   DOUT << "\t\tregister with min weight: "
-       << tri_->getPrintableName(minReg) << " (" << minWeight << ")\n";
+       << tri_->getName(minReg) << " (" << minWeight << ")\n";
 
   // if the current has the minimum weight, we need to spill it and
   // add any added intervals back to unhandled, and restart
@@ -869,11 +869,11 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   if (cur->preference) {
     if (prt_->isRegAvail(cur->preference)) {
       DOUT << "\t\tassigned the preferred register: "
-           << tri_->getPrintableName(cur->preference) << "\n";
+           << tri_->getName(cur->preference) << "\n";
       return cur->preference;
     } else
       DOUT << "\t\tunable to assign the preferred register: "
-           << tri_->getPrintableName(cur->preference) << "\n";
+           << tri_->getName(cur->preference) << "\n";
   }
 
   // Scan for the first available register.

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index bcadf89fe5c9792bd54e4ee173fd25eb5bcb14da..99fc6c9028ab7ba4a6d9b3e55c8af02570ba3e2e 100644 (file)
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -286,7 +286,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
   assert(VirtReg && "Spilling a physical register is illegal!"
          " Must not have appropriate kill for the register or use exists beyond"
          " the intended one.");
-  DOUT << "  Spilling register " << TRI->getPrintableName(PhysReg)
+  DOUT << "  Spilling register " << TRI->getName(PhysReg)
        << " containing %reg" << VirtReg;
   
   const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@@ -502,7 +502,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
   markVirtRegModified(VirtReg, false);   // Note that this reg was just reloaded
 
   DOUT << "  Reloading %reg" << VirtReg << " into "
-       << TRI->getPrintableName(PhysReg) << "\n";
+       << TRI->getName(PhysReg) << "\n";
 
   // Add move instruction(s)
   const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@@ -575,7 +575,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
           DOUT << "  Regs have values: ";
           for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
             if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
-               DOUT << "[" << TRI->getPrintableName(i)
+               DOUT << "[" << TRI->getName(i)
                     << ",%reg" << PhysRegsUsed[i] << "] ";
           DOUT << "\n");
 
@@ -637,14 +637,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT << "  Last use of " << TRI->getPrintableName(PhysReg)
+        DOUT << "  Last use of " << TRI->getName(PhysReg)
              << "[%reg" << VirtReg <<"], removing it from live set\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
             DOUT  << "  Last use of "
-                  << TRI->getPrintableName(*AliasSet)
+                  << TRI->getName(*AliasSet)
                   << "[%reg" << VirtReg <<"], removing it from live set\n";
             removePhysReg(*AliasSet);
           }
@@ -728,7 +728,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
         MF->getRegInfo().setPhysRegUsed(DestPhysReg);
         markVirtRegModified(DestVirtReg);
         getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
-        DOUT << "  Assigning " << TRI->getPrintableName(DestPhysReg)
+        DOUT << "  Assigning " << TRI->getName(DestPhysReg)
              << " to %reg" << DestVirtReg << "\n";
         MI->getOperand(i).setReg(DestPhysReg);  // Assign the output register
       }
@@ -751,14 +751,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT  << "  Register " << TRI->getPrintableName(PhysReg)
+        DOUT  << "  Register " << TRI->getName(PhysReg)
               << " [%reg" << VirtReg
               << "] is never used, removing it frame live list\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
-            DOUT  << "  Register " << TRI->getPrintableName(*AliasSet)
+            DOUT  << "  Register " << TRI->getName(*AliasSet)
                   << " [%reg" << *AliasSet
                   << "] is never used, removing it frame live list\n";
             removePhysReg(*AliasSet);

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index cbc54cc54b101cc32ff01342b63d68c2f39c216f..a6226d8cf2760cacad7b87df65426b778235ded9 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4181,8 +4181,7 @@ void SDNode::dump(const SelectionDAG *G) const {
   } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
     if (G && R->getReg() &&
         TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
-      cerr << " "
-           << G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
+      cerr << " " << G->getTarget().getRegisterInfo()->getName(R->getReg());
     } else {
       cerr << " #" << R->getReg();
     }

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 73871863339a96c3b9b52cd243807ffab7f61fb5..d8230be3c343ad1a7c25857fe3c7e6d1af0c284c 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -134,7 +134,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
     if (G && R->getReg() != 0 &&
         TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
       Op = Op + " " +
-       G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
+       G->getTarget().getRegisterInfo()->getName(R->getReg());
     } else {
       Op += " #" + utostr(R->getReg());
     }

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 3d777e39c4bb4760910f5582fa46729dce8ad359..f015ad5c1f391d35820b1bbde76e3fcba358673d 100644 (file)
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1537,7 +1537,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
 
 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
   if (TargetRegisterInfo::isPhysicalRegister(reg))
-    cerr << tri_->getPrintableName(reg);
+    cerr << tri_->getName(reg);
   else
     cerr << "%reg" << reg;
 }

diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 93a584b7a9b0ddd64c2528238d9419fd380ede81..fe81fdd9366401c4bcf9f1fdda034b067a54ebe5 100644 (file)
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -141,7 +141,7 @@ void VirtRegMap::print(std::ostream &OS) const {
   for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
          e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
     if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
-      OS << "[reg" << i << " -> " << TRI->getPrintableName(Virt2PhysMap[i])
+      OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
          << "]\n";
   }
 
@@ -351,7 +351,7 @@ public:
       DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
     else
       DOUT << "Remembering SS#" << SlotOrReMat;
-    DOUT << " in physreg " << TRI->getPrintableName(Reg) << "\n";
+    DOUT << " in physreg " << TRI->getName(Reg) << "\n";
   }
 
   /// canClobberPhysReg - Return true if the spiller is allowed to change the 
@@ -392,7 +392,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
     assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
            "Bidirectional map mismatch!");
     SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
-    DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
+    DOUT << "PhysReg " << TRI->getName(PhysReg)
          << " copied, it is available for use but can no longer be modified\n";
   }
 }
@@ -417,7 +417,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
     assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
            "Bidirectional map mismatch!");
     SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
-    DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
+    DOUT << "PhysReg " << TRI->getName(PhysReg)
          << " clobbered, invalidating ";
     if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
       DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
@@ -1135,9 +1135,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
           else
             DOUT << "Reusing SS#" << ReuseSlot;
           DOUT << " from physreg "
-               << TRI->getPrintableName(PhysReg) << " for vreg"
+               << TRI->getName(PhysReg) << " for vreg"
                << VirtReg <<" instead of reloading into physreg "
-               << TRI->getPrintableName(VRM.getPhys(VirtReg)) << "\n";
+               << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
           unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
           MI.getOperand(i).setReg(RReg);
 
@@ -1208,7 +1208,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
             DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
           else
             DOUT << "Reusing SS#" << ReuseSlot;
-          DOUT << " from physreg " << TRI->getPrintableName(PhysReg)
+          DOUT << " from physreg " << TRI->getName(PhysReg)
               << " for vreg" << VirtReg
                << " instead of reloading into same physreg.\n";
           unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index b050debb46c9b992e0fd29ab2793f47d7785e970..3481414c7a895ebe72f20c49985a6280a93c017c 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -334,6 +334,6 @@ int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 
 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
 {
-  std::string s(RegisterDescriptors[reg].PrintableName);
+  std::string s(RegisterDescriptors[reg].Name);
   return s;
 }

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 3d55969dd039a17c517a4768b83f568bc7435c0b..b71e580d7eeebcea615b0f5e1d4b959b1443d6ac 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -25,7 +25,7 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
 class GP8<GPR SubReg, string n> : PPCReg<SubReg.AsmName> {
   field bits<5> Num = SubReg.Num;
   let SubRegs = [SubReg];
-  let PrintableName = n;
+  let Name = n;
 }
 
 // SPR - One of the 32-bit special-purpose registers

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 47efd5eb2b6f46120a7afbdac2c770d40e556e19..cebac7a263650b8b01f7ea5043b73025fe7a3c74 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -26,7 +26,7 @@ class RegisterClass; // Forward def
 class Register<string n> {
   string Namespace = "";
   string AsmName = n;
-  string PrintableName = n;
+  string Name = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in
   // bits of the spill slot required to hold this register.  If this value is

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index cf41dd271af2a9b578ec51577f64ec56519841c5..c9f8d0ac220b8f73945692ecba7e94527382008a 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -525,12 +525,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     else
       OS << Reg.getName();
     OS << "\",\t\"";
-    if (!Reg.TheDef->getValueAsString("PrintableName").empty()) {
-      OS << Reg.TheDef->getValueAsString("PrintableName");
+    if (!Reg.TheDef->getValueAsString("Name").empty()) {
+      OS << Reg.TheDef->getValueAsString("Name");
     } else {
       // Default to "name".
-      if (!Reg.TheDef->getValueAsString("Name").empty())
-        OS << Reg.TheDef->getValueAsString("Name");
+      if (!Reg.TheDef->getValueAsString("AsmName").empty())
+        OS << Reg.TheDef->getValueAsString("AsmName");
       else
         OS << Reg.getName();
     }