if ((open) && (!lcdc_dev->atv_layer_cnt)) {
rk3036_lcdc_pre_init(dev_drv);
rk3036_lcdc_clk_enable(lcdc_dev);
- #if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!dev_drv->mmu_dev) {
dev_drv->mmu_dev =
}
}
}
- #endif
rk3036_lcdc_reg_restore(lcdc_dev);
/*if (dev_drv->iommu_enabled)
rk3036_lcdc_mmu_en(dev_drv);*/
if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
rk3036_lcdc_disable_irq(lcdc_dev);
rk3036_lcdc_reg_update(dev_drv);
- #if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (dev_drv->mmu_dev)
rockchip_iovmm_deactivate(dev_drv->dev);
}
- #endif
rk3036_lcdc_clk_disable(lcdc_dev);
}
*/
spin_lock(&lcdc_dev->reg_lock);
if (lcdc_dev->clk_on) {
- #if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
lcdc_dev->iommu_status = 1;
rk3036_lcdc_mmu_en(dev_drv);
}
}
- #endif
lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
v_LCDC_STANDBY(lcdc_dev->standby));
for (i = 0; i < ARRAY_SIZE(lcdc_win); i++) {
struct device_node *np = lcdc_dev->dev->of_node;
int val;
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
lcdc_dev->driver.iommu_enabled = 0;
else
lcdc_dev->driver.iommu_enabled = val;
-#else
- lcdc_dev->driver.iommu_enabled = 0;
-#endif
if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
else
lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
}
/*spin_unlock(&lcdc_dev->reg_lock);*/
- #if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
lcdc_dev->iommu_status = 1;
rockchip_iovmm_activate(dev_drv->dev);
}
}
- #endif
return 0;
}
rockchip_set_system_status(SYS_STATUS_LCDC0);
rk312x_lcdc_pre_init(dev_drv);
rk312x_lcdc_clk_enable(lcdc_dev);
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!dev_drv->mmu_dev) {
dev_drv->mmu_dev =
/*if (dev_drv->mmu_dev)
rockchip_iovmm_activate(dev_drv->dev);*/
}
-#endif
rk312x_lcdc_reg_restore(lcdc_dev);
/*if (dev_drv->iommu_enabled)
rk312x_lcdc_mmu_en(dev_drv);*/
/* if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
rk312x_lcdc_disable_irq(lcdc_dev);
rk312x_lcdc_reg_update(dev_drv);
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (dev_drv->mmu_dev)
rockchip_iovmm_deactivate(dev_drv->dev);
}
-#endif
rk312x_lcdc_clk_disable(lcdc_dev);
rockchip_clear_system_status(SYS_STATUS_LCDC0);
}*/
const struct rk_lcdc_drvdata *lcdc_drvdata;
int val;
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
lcdc_dev->driver.iommu_enabled = 0;
else
lcdc_dev->driver.iommu_enabled = val;
-#else
- lcdc_dev->driver.iommu_enabled = 0;
-#endif
if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
return 0;
}
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!vop_dev->iommu_status && dev_drv->mmu_dev) {
if (likely(vop_dev->clk_on)) {
rockchip_iovmm_activate(dev_drv->dev);
}
}
-#endif
return 0;
}
vop_pre_init(dev_drv);
vop_clk_enable(vop_dev);
vop_enable_irq(dev_drv);
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!dev_drv->mmu_dev) {
dev_drv->mmu_dev =
}
}
}
-#endif
if ((support_uboot_display() && (vop_dev->prop == PRMRY)))
vop_set_dclk(dev_drv, 0);
else
dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
}
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
dev_drv->iommu_enabled = 0;
else
dev_drv->iommu_enabled = val;
-#else
- dev_drv->iommu_enabled = 0;
-#endif
return 0;
}
pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
return 0;
}
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
rockchip_iovmm_activate(dev_drv->dev);
}
}
-#endif
return 0;
}
rk3288_lcdc_pre_init(dev_drv);
rk3288_lcdc_clk_enable(lcdc_dev);
rk3288_lcdc_enable_irq(dev_drv);
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (!dev_drv->mmu_dev) {
dev_drv->mmu_dev =
}
}
}
-#endif
rk3288_lcdc_reg_restore(lcdc_dev);
/*if (dev_drv->iommu_enabled)
rk3368_lcdc_mmu_en(dev_drv); */
if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
rk3288_lcdc_disable_irq(lcdc_dev);
rk3288_lcdc_reg_update(dev_drv);
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (dev_drv->iommu_enabled) {
if (dev_drv->mmu_dev) {
rockchip_iovmm_deactivate(dev_drv->dev);
lcdc_dev->iommu_status = 0;
}
}
-#endif
rk3288_lcdc_clk_disable(lcdc_dev);
rockchip_clear_system_status(sys_status);
}
dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
}
-#if defined(CONFIG_ROCKCHIP_IOMMU)
if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
dev_drv->iommu_enabled = 0;
else
dev_drv->iommu_enabled = val;
-#else
- dev_drv->iommu_enabled = 0;
-#endif
return 0;
}
pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
return 0;
}
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
if (likely(lcdc_dev->clk_on)) {
rockchip_iovmm_activate(dev_drv->dev);
}
}
-#endif
return 0;
}
rk3368_lcdc_pre_init(dev_drv);
rk3368_lcdc_clk_enable(lcdc_dev);
rk3368_lcdc_enable_irq(dev_drv);
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
if (!dev_drv->mmu_dev) {
dev_drv->mmu_dev =
/*if (dev_drv->mmu_dev)
rockchip_iovmm_activate(dev_drv->dev); */
}
-#endif
rk3368_lcdc_reg_restore(lcdc_dev);
/*if (dev_drv->iommu_enabled)
rk3368_lcdc_mmu_en(dev_drv); */
/*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
rk3368_lcdc_disable_irq(lcdc_dev);
rk3368_lcdc_reg_update(dev_drv);
- #if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
if (dev_drv->mmu_dev)
rockchip_iovmm_deactivate(dev_drv->dev);
}
- #endif
rk3368_lcdc_clk_disable(lcdc_dev);
#ifndef CONFIG_RK_FPGA
rockchip_clear_system_status(sys_status);
dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
}
-#if defined(CONFIG_RK_IOMMU)
if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
dev_drv->iommu_enabled = 0;
else
dev_drv->iommu_enabled = val;
-#else
- dev_drv->iommu_enabled = 0;
-#endif
return 0;
}
Rga_Request.clip.ymin = 0;
Rga_Request.clip.ymax = dst_win->area[0].yact - 1;
Rga_Request.scale_mode = 0;
-#if defined(CONFIG_RK_IOMMU)
if (iommu_en) {
Rga_Request.mmu_info.mmu_en = 1;
Rga_Request.mmu_info.mmu_flag = 1;
Rga_Request.mmu_info.mmu_en = 0;
Rga_Request.mmu_info.mmu_flag = 0;
}
-#else
- Rga_Request.mmu_info.mmu_en = 0;
- Rga_Request.mmu_info.mmu_flag = 0;
-#endif
ret = rga_ioctl_kernel(&Rga_Request);
}
return 0;
}
#endif
-#ifdef CONFIG_RK_IOMMU
static int g_last_addr[5][4];
static int g_now_config_addr[5][4];
static int g_last_state[5][4];
return 0;
}
-#endif
void rk_fb_free_dma_buf(struct rk_lcdc_driver *dev_drv,
struct rk_fb_reg_win_data *reg_win_data)
for (i = 0; i < reg_win_data->area_num; i++) {
area_data = ®_win_data->reg_area_data[i];
index_buf = area_data->index_buf;
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
if (area_data->ion_handle != NULL &&
!IS_YUV_FMT(area_data->data_format))
area_data->ion_handle);
freed_addr[freed_index++] = area_data->smem_start;
}
-#endif
if (area_data->ion_handle != NULL)
ion_free(rk_fb->ion_client, area_data->ion_handle);
win->area[i].y_vir_stride =
reg_win_data->reg_area_data[i].y_vir_stride;
win->area[i].state = 1;
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
g_now_config_addr[win->id][i] =
win->area[i].smem_start +
win->area[i].y_offset;
g_now_config_state[win->id][i] = 1;
}
-#endif
} else {
win->area[i].state = 0;
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
g_now_config_addr[win->id][i] = 0;
g_now_config_state[win->id][i] = 0;
}
-#endif
}
}
}
win->state = 0;
for (j = 0; j < 4; j++)
win->area[j].state = 0;
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
for (j = 0; j < 4; j++) {
g_now_config_addr[i][j] = 0;
g_now_config_state[i][j] = 0;
}
}
-#endif
}
}
dev_drv->ops->ovl_mgr(dev_drv, 0, 1);
#endif
if (dev_drv->front_regs) {
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
if (dev_drv->ops->mmu_en)
dev_drv->ops->mmu_en(dev_drv);
freed_index = 0;
g_last_timeout = timeout;
}
-#endif
mutex_lock(&dev_drv->front_lock);
mutex_unlock(&dev_drv->front_lock);
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled)
freed_addr[freed_index] = 0xfefefefe;
-#endif
}
mutex_lock(&dev_drv->front_lock);
break;
}
reg_win_data->reg_area_data[i].ion_handle = hdl;
-#ifndef CONFIG_RK_IOMMU
- ret = ion_phys(rk_fb->ion_client, hdl, &phy_addr,
- &len);
-#else
if (dev_drv->iommu_enabled)
ret = ion_map_iommu(dev_drv->dev,
rk_fb->ion_client,
else
ret = ion_phys(rk_fb->ion_client, hdl,
&phy_addr, &len);
-#endif
if (ret < 0) {
dev_err(fbi->dev, "ion map to get phy addr failed\n");
ion_free(rk_fb->ion_client, hdl);
EXPORT_SYMBOL(rk_get_real_fps);
#endif
-#ifdef CONFIG_RK_IOMMU
#define ION_MAX 10
static struct ion_handle *ion_hanle[ION_MAX];
static struct ion_handle *ion_hwc[1];
-#endif
static int rk_fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
if (copy_from_user(hwc_phy, argp, 4))
return -EFAULT;
-#ifdef CONFIG_RK_IOMMU
if (!dev_drv->iommu_enabled) {
-#endif
fix->smem_start = hwc_phy[0];
-#ifdef CONFIG_RK_IOMMU
} else {
int usr_fd;
struct ion_handle *hdl;
fix->smem_start = phy_addr;
ion_hwc[0] = hdl;
}
-#endif
break;
}
case RK_FBIOSET_YUV_ADDR:
if (copy_from_user(yuv_phy, argp, 8))
return -EFAULT;
- #ifdef CONFIG_RK_IOMMU
if (!dev_drv->iommu_enabled || !strcmp(info->fix.id, "fb0")) {
- #endif
fix->smem_start = yuv_phy[0];
fix->mmio_start = yuv_phy[1];
- #ifdef CONFIG_RK_IOMMU
} else {
int usr_fd, offset, tmp;
struct ion_handle *hdl;
ion_hanle[tmp] = ion_hanle[tmp - 1];
ion_hanle[0] = 0;
}
- #endif
break;
}
case RK_FBIOSET_ENABLE:
win->area[0].ion_hdl = handle;
if (dev_drv->prop == PRMRY)
fbi->screen_base = ion_map_kernel(rk_fb->ion_client, handle);
-#ifdef CONFIG_RK_IOMMU
if (dev_drv->iommu_enabled && dev_drv->mmu_dev)
ret = ion_map_iommu(dev_drv->dev, rk_fb->ion_client, handle,
(unsigned long *)&phy_addr,
(unsigned long *)&len);
else
ret = ion_phys(rk_fb->ion_client, handle, &phy_addr, &len);
-#else
- ret = ion_phys(rk_fb->ion_client, handle, &phy_addr, &len);
-#endif
if (ret < 0) {
dev_err(fbi->dev, "ion map to get phy addr failed\n");
goto err_share_dma_buf;
fb_par->ion_hdl);
dev_drv->win[win_id]->area[0].ion_hdl =
fb_par->ion_hdl;
-#ifdef CONFIG_RK_IOMMU
- if (dev_drv->mmu_dev)
+ if (dev_drv->iommu_enabled && dev_drv->mmu_dev)
ret = ion_map_iommu(dev_drv->dev,
rk_fb->ion_client,
fb_par->ion_hdl,
ret = ion_phys(rk_fb->ion_client,
fb_par->ion_hdl,
&phy_addr, &len);
-#endif
if (ret < 0) {
dev_err(fbi->dev, "ion map to get phy addr failed\n");
return -ENOMEM;
main_fbi->fbops->fb_open(main_fbi, 1);
main_fbi->var.pixclock = dev_drv->pixclock;
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
if (dev_drv->mmu_dev)
rockchip_iovmm_set_fault_handler(dev_drv->dev,
rk_fb_sysmmu_fault_handler);
}
-#endif
rk_fb_alloc_buffer(main_fbi); /* only alloc memory for main fb */
dev_drv->uboot_logo = support_uboot_display();
#endif
} else {
struct fb_info *extend_fbi = rk_fb->fb[rk_fb->num_fb >> 1];
-
extend_fbi->var.pixclock = rk_fb->fb[0]->var.pixclock;
extend_fbi->fbops->fb_open(extend_fbi, 1);
-#if defined(CONFIG_RK_IOMMU)
if (dev_drv->iommu_enabled) {
if (dev_drv->mmu_dev)
rockchip_iovmm_set_fault_handler(dev_drv->dev,
rk_fb_sysmmu_fault_handler);
}
-#endif
rk_fb_alloc_buffer(extend_fbi);
}
#endif