PowerPC cannot truncstore i1 natively

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23304 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 0ae7ad6b4fbd03423290c9858ea854e0ee77c09f..e342d71921e6dd2c8d467f4c3c2331f77f55941f 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1263,7 +1263,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     } else { //ISD::TRUNCSTORE
       switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
       default: assert(0 && "unknown Type in store");
-      case MVT::i1:
       case MVT::i8:  Opc = isIdx ? PPC::STBX : PPC::STB; break;
       case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
       }

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index bf8dbed006d06093edc70d85e900071c1aa8e011..340c0a478ad9f492adf465fccd92d21fbc5d644a 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -91,6 +91,9 @@ PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
 
+  // PowerPC does not have truncstore for i1.
+  setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
+  
   // 64 bit PowerPC implementations have instructions to facilitate conversion
   // between i64 and fp.
   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 2cb3d8fbd1ece3f08199d8e967dcaff9325ee644..73e9e2f4dbc2dd6c4e3f2d21bbec4776df33f077 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1795,7 +1795,6 @@ void ISel::Select(SDOperand N) {
     } else { //ISD::TRUNCSTORE
       switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
       default: assert(0 && "unknown Type in store");
-      case MVT::i1:
       case MVT::i8: Opc  = PPC::STB; break;
       case MVT::i16: Opc = PPC::STH; break;
       }