[mips] Remap move as or.

Summary:
This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.

This patch preserves the disassembly behaviour so that disassembling a old style
(d)addu move still appears as move, but assembling move always gives an or

Patch by Simon Dardis.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244579 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 8e6c9e69b223dea5a81d5a86a251d15f209eff18..14c5a34602af87b495c2c8214d86f802108aa97e 100644 (file)
--- a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -115,6 +115,10 @@ unsigned MipsABIInfo::GetPtrAddiuOp() const {
   return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
 }
 
+unsigned MipsABIInfo::GetGPRMoveOp() const {
+  return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
+}
+
 unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
   static const unsigned EhDataReg[] = {
     Mips::A0, Mips::A1, Mips::A2, Mips::A3

diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
index 40c5681acc17b1d8620b558e3119ef8eced5b0b7..926da905cb611fa46148665dc61d586b429622b8 100644 (file)
--- a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
@@ -69,6 +69,7 @@ public:
   unsigned GetNullPtr() const;
   unsigned GetPtrAdduOp() const;
   unsigned GetPtrAddiuOp() const;
+  unsigned GetGPRMoveOp() const;
   inline bool ArePtrs64bit() const { return IsN64(); }
 
   unsigned GetEhDataReg(unsigned I) const;

diff --git a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index e4da2df75d477f81ba3444ef0137055edb7428fa..dc4673d365d17f94ad232ca2eca0efd98ba8b707 100644 (file)
--- a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -766,7 +766,7 @@ void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
   // Either store the old $gp in a register or on the stack
   if (IsReg) {
     // move $save, $gpreg
-    Inst.setOpcode(Mips::DADDu);
+    Inst.setOpcode(Mips::OR64);
     Inst.addOperand(MCOperand::createReg(RegOrOffset));
     Inst.addOperand(MCOperand::createReg(Mips::GP));
     Inst.addOperand(MCOperand::createReg(Mips::ZERO));

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index f917ecad4a534f7da6b13691735896aa839bb993..1d18f4d0db9dd302719550daba01ade7db8955d3 100644 (file)
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -547,6 +547,9 @@ def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
+def : MipsInstAlias<"move $dst, $src",
+                    (OR64 GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
+      GPR_64;
 def : MipsInstAlias<"move $dst, $src",
                     (DADDu GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
       GPR_64;

diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 027c4e2a5ed6aa04c6bd2bd976b58f87164d1dc2..88b54b5209dd38c3746d87afae55b6f5c91de5ae 100644 (file)
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -1008,7 +1008,7 @@ void MipsAsmPrinter::EmitFPCallStub(
   //
   // Mov $18, $31
 
-  EmitInstrRegRegReg(*STI, Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
+  EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
 
   EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
 

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 0862285941fa436339346ffb3b8ab3642b158c12..45eb35698c09eca0a74eba3821836e5cdfa18ebc 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1570,7 +1570,12 @@ def PREF :  MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
-                    (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
+                    (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
+      GPR_32 {
+  let AdditionalPredicates = [NotInMicroMips];
+}
+def : MipsInstAlias<"move $dst, $src",
+                    (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
       GPR_32 {
   let AdditionalPredicates = [NotInMicroMips];
 }

diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp
index a19d1504e1e0e7f796ff380316c2d28389f8b5ec..5b4608fad2b83b32e448ef583842fc9b0814d9b7 100644 (file)
--- a/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -381,7 +381,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
   unsigned ZERO = ABI.GetNullPtr();
-  unsigned ADDu = ABI.GetPtrAdduOp();
+  unsigned MOVE = ABI.GetGPRMoveOp();
   unsigned ADDiu = ABI.GetPtrAddiuOp();
   unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
 
@@ -491,7 +491,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
   // if framepointer enabled, set it to point to the stack pointer.
   if (hasFP(MF)) {
     // Insert instruction "move $fp, $sp" at this location.
-    BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
+    BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
       .setMIFlag(MachineInstr::FrameSetup);
 
     // emit ".cfi_def_cfa_register $fp"
@@ -514,7 +514,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
       if (hasBP(MF)) {
         // move $s7, $sp
         unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
-        BuildMI(MBB, MBBI, dl, TII.get(ADDu), BP)
+        BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)
           .addReg(SP)
           .addReg(ZERO);
       }
@@ -538,7 +538,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
   unsigned ZERO = ABI.GetNullPtr();
-  unsigned ADDu = ABI.GetPtrAdduOp();
+  unsigned MOVE = ABI.GetGPRMoveOp();
 
   // if framepointer enabled, restore the stack pointer.
   if (hasFP(MF)) {
@@ -549,7 +549,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
       --I;
 
     // Insert instruction "move $sp, $fp" at this location.
-    BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
+    BuildMI(MBB, I, dl, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
   }
 
   if (MipsFI->callsEhReturn()) {

diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp
index 786307b95f881585df43655ad10b7ed9897e57d8..938285f2e519cd15a50ad0e78338bf0749f80ea8 100644 (file)
--- a/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -88,7 +88,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       if (isMicroMips)
         Opc = Mips::MOVE16_MM;
       else
-        Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
+        Opc = Mips::OR, ZeroReg = Mips::ZERO;
     } else if (Mips::CCRRegClass.contains(SrcReg))
       Opc = Mips::CFC1;
     else if (Mips::FGR32RegClass.contains(SrcReg))
@@ -141,7 +141,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     Opc = Mips::FMOV_D64;
   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
     if (Mips::GPR64RegClass.contains(SrcReg))
-      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
+      Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
     else if (Mips::HI64RegClass.contains(SrcReg))
       Opc = Mips::MFHI64, SrcReg = 0;
     else if (Mips::LO64RegClass.contains(SrcReg))

diff --git a/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt b/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
index dba949acd66ae24c9f7f5d846a4fb0e3c53f5c18..869d909621a194d533e030623b07058e835f8648 100644 (file)
--- a/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
+++ b/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
@@ -58,6 +58,8 @@
 0x12 0x88 0x00 0x00 # CHECK: mflo $17
 0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9

diff --git a/test/MC/Disassembler/Mips/mips1/valid-mips1.txt b/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
index 59e702e17e1c695a79b42eb070dc0d26c10b8d71..5c4c5612e8460c4a85eed5b0d86a4312bb093779 100644 (file)
--- a/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
+++ b/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
@@ -16,11 +16,13 @@
 0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
 0x01 0x32 0x00 0x19 # CHECK: multu $9, $18

diff --git a/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt b/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
index 806040937b77a536b0bf7d8ebf4f34ba0b0dbbb8..5bdf8f17eb68e8e97d0f749c01d2fe247ebd11a6 100644 (file)
--- a/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
+++ b/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
@@ -74,6 +74,8 @@
 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
 0x11 0x00 0x20 0x02 # CHECK: mthi $17
 0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp

diff --git a/test/MC/Disassembler/Mips/mips2/valid-mips2.txt b/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
index 268bb290090341a20c0210eb1140394ea5f7d493..f3b67842a0140b25fcfdd5583f0f67118f1c3350 100644 (file)
--- a/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
+++ b/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
@@ -19,6 +19,7 @@
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
@@ -26,6 +27,7 @@
 0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10

diff --git a/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt b/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
index 98ce16bb7429f9dac49ee24d17aa275b54a46de7..6ffe7748e950e78f612c2685f846e3c65e65c6ba 100644 (file)
--- a/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
+++ b/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
@@ -118,6 +118,8 @@
 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
 0x11 0x00 0x20 0x02 # CHECK: mthi $17
 0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp

diff --git a/test/MC/Disassembler/Mips/mips3/valid-mips3.txt b/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
index 2a38b19092f08b1c318c263d6223f29fab3e0416..81888588e69d3bf7a44689a17dfd2b08b0df5d2b 100644 (file)
--- a/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
+++ b/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
@@ -35,6 +35,8 @@
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x2d # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
@@ -44,6 +46,8 @@
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x2d # CHECK: move $25, $6
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10

diff --git a/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt b/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
index f2299732a80e5a680e5ae035a9881ebd34dc37ed..84ff39c8fc9ea9b46c70106954fe0f0884fe4f1f 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
+++ b/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
@@ -7,7 +7,9 @@
 0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
 0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
 0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332

diff --git a/test/MC/Disassembler/Mips/mips32/valid-mips32.txt b/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
index 09f1e56fff43af6453097ac9dde94ea035e4555d..00c910b484e8301d28ed5ac571a244b35341be4e 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
+++ b/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
@@ -15,6 +15,8 @@
 0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
 0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5

diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
index c019c41bd12027224208ee9ffd6992a6c456df0d..cdc69a7b1edab0ea83400dafae3b841aa1662d6a 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32_le.txt
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -273,7 +273,7 @@
 0x86 0x39 0x00 0x46
 
 # CHECK: move $7, $8
-0x21,0x38,0x00,0x01
+0x25,0x38,0x00,0x01
 
 # CHECK: move $3, $2
 0x25,0x18,0x40,0x00

diff --git a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
index d01384752907d9a98aa0d68d84515fa03fbd8b7c..80615b889fc53ed1a62e01f8517e5e5d5612d97d 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -17,6 +17,8 @@
 0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
 0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5

diff --git a/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt b/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
index 0c9e2f1b742f7770758d499911dba443eb8c1f0d..1d1044d32055cb6397c1d4a53c80f4fde761cc24 100644 (file)
--- a/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
+++ b/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
@@ -126,6 +126,8 @@
 0xd1 0x2d 0x18 0x46 # CHECK: movf.s $f23, $f5, $fcc6
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x0b 0x18 0x30 0x02 # CHECK: movn $3, $17, $16
 0xd3 0xae 0x3a 0x46 # CHECK: movn.d $f27, $f21, $26
 0x13 0x03 0x17 0x46 # CHECK: movn.s $f12, $f0, $23

diff --git a/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
index 207f4087791dfa913156b9391dd5c4662d24ae26..7dad85aa3cdab22eb555b9d506155a92b8831c65 100644 (file)
--- a/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ b/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -35,6 +35,8 @@
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x2d # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
@@ -44,6 +46,8 @@
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x2d # CHECK: move $25, $6
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10

diff --git a/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt b/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
index 2d52216fddaada99b18c05a482e7767f3a2fc555..e1b272962c8d3eba586cb672c0fc7b8ca918f92c 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
+++ b/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
@@ -148,6 +148,8 @@
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

diff --git a/test/MC/Disassembler/Mips/mips64/valid-mips64.txt b/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
index 6cbf5d3206b020d06123baf85178fc78a786d234..0013dec7e716dcc9323a4e015666bde08dacfad0 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
+++ b/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
@@ -67,6 +67,8 @@
 0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
 0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24
 0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328

diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
index 2c6859f27faa6d6f743687a139abb2f2e84fe3e7..c3e24820a17c63fc2710c07fd269783f6e8d7830 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -168,6 +168,8 @@
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CHECK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
index 0c6e10ee37ce6e8a0ce5ac9d3cd5245cb81a33e2..431cbedff88b370111c6ba957bb6b5730b7bf4a4 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -80,6 +80,8 @@
 0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
 0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24
 0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328

diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
index 88e9c262a0eeaae8cae80695931c55de0163150a..7d59ef6d3e03b69c2913e352be71cefb27f6bb77 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -165,6 +165,8 @@
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
index 82405f357bf4dfea7b94da682fff571fdef64493..72996522949eedec68bf6ad1391818ac015f2028 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -63,6 +63,8 @@
 0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328

diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
index bd709d2287940879c6af1bacf2143b4ade2fc7ea..ee6ad1c719457d5a60ea3020da3ed06963cedb38 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -165,6 +165,8 @@
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
index a27fa98c96317cad52ba45c5b8c9f1268501e14c..4b1810b59e0a10894639b051d5f9dbe897f27dab 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -63,6 +63,8 @@
 0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328

diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
index 157e33593e37d527989a3599f7a891d6e6babfeb..b2bbc64330d9ae2e2ad073ead5023449c1327cbe 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -128,6 +128,8 @@
 0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
+0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CHECK: move $15, $ra
 0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4

diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 5be21256d28685e17810a980c6f0829bc7bfaaee..e6378d24c574d37cf4808aad87f3ba29f11b4f53 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -45,6 +45,8 @@
 0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0x11 0x14 0x9b # CHECK: bal 21104
 0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
 0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555

diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
index b25394b39a67763286d71ea9ca84bd22a5a6e0f1..9c133abbae366a3eba7464ece7155ec2b45bf630 100644 (file)
--- a/test/MC/Mips/mips-alu-instructions.s
+++ b/test/MC/Mips/mips-alu-instructions.s
@@ -91,7 +91,7 @@
 # CHECK:  addiu   $sp, $sp, -40  # encoding: [0xd8,0xff,0xbd,0x27]
 # CHECK:  neg     $6, $7         # encoding: [0x22,0x30,0x07,0x00]
 # CHECK:  negu    $6, $7         # encoding: [0x23,0x30,0x07,0x00]
-# CHECK:  move    $7, $8         # encoding: [0x21,0x38,0x00,0x01]
+# CHECK:  move    $7, $8         # encoding: [0x25,0x38,0x00,0x01]
 # CHECK:  .set    push
 # CHECK:  .set    mips32r2
 # CHECK:  rdhwr   $5, $29

diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s
index e2feeac4dd56e69259fe9ab5f5861d248878273b..80f0f8b047c6e3ada932b5d83e6158a6d7d70e7a 100644 (file)
--- a/test/MC/Mips/mips1/valid.s
+++ b/test/MC/Mips/mips1/valid.s
@@ -64,8 +64,8 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4           # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6           # encoding: [0x00,0xc0,0xc8,0x25]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp

diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s
index 93fdbafdfcd0901282c2f32af571d982b781be60..c57d386d9d05dc86425abb479e5dc318b1713d3a 100644 (file)
--- a/test/MC/Mips/mips2/valid.s
+++ b/test/MC/Mips/mips2/valid.s
@@ -84,8 +84,8 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp

diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s
index 1c878c97d158efb4f463a2d465aa0dabdf44ed85..cf51753712e6fc0022a5e892877f91877ddd4e30 100644 (file)
--- a/test/MC/Mips/mips3/valid.s
+++ b/test/MC/Mips/mips3/valid.s
@@ -142,10 +142,10 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp

diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s
index fbe1551f6c2611a06e89c78fdeb5d98499f8d010..6958583030a773198529273a229d5d5090c86fb8 100644 (file)
--- a/test/MC/Mips/mips32/valid.s
+++ b/test/MC/Mips/mips32/valid.s
@@ -96,8 +96,8 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s
index 2e4366ab40f1c710328ee7c53c39f123778976fe..cd1b749a57ea7e78df0bd5ced9dbf43fc4ce8e20 100644 (file)
--- a/test/MC/Mips/mips32r2/valid.s
+++ b/test/MC/Mips/mips32r2/valid.s
@@ -111,8 +111,8 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips32r3/valid.s b/test/MC/Mips/mips32r3/valid.s
index f6ef1d356c1fc7ec837b9841484d3f942e567c99..f983051c9a640c674d06f56278b79dce1cbb49ce 100644 (file)
--- a/test/MC/Mips/mips32r3/valid.s
+++ b/test/MC/Mips/mips32r3/valid.s
@@ -111,8 +111,8 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s
index 3bb8e84ffe0fb262aefe72991a5ff52c4fd704c4..e0b6db6e38fc927ff2fb0a89def86b0c11bdc18c 100644 (file)
--- a/test/MC/Mips/mips32r5/valid.s
+++ b/test/MC/Mips/mips32r5/valid.s
@@ -112,8 +112,8 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s
index 073da85dfde944d06c4d0a2bcafebb681cea5dc5..02805089130754d74377e385cbf67126fcfeb7dd 100644 (file)
--- a/test/MC/Mips/mips32r6/valid.s
+++ b/test/MC/Mips/mips32r6/valid.s
@@ -113,6 +113,10 @@ a:
         mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1  # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        move    $a0,$a3          # CHECK: move $4, $7      # encoding: [0x00,0xe0,0x20,0x25]
+        move    $s5,$a0          # CHECK: move $21, $4     # encoding: [0x00,0x80,0xa8,0x25]
+        move    $s8,$a0          # CHECK: move $fp, $4     # encoding: [0x00,0x80,0xf0,0x25]
+        move    $25,$a2          # CHECK: move $25, $6     # encoding: [0x00,0xc0,0xc8,0x25]
         mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1  # encoding: [0x40,0x89,0x78,0x01]
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]

diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s
index b89026dd714a09c5d402a36167e73466a51c52a5..9bf98d1c29ff1130132c55e17ee8d74873b7f1ca 100644 (file)
--- a/test/MC/Mips/mips4/valid.s
+++ b/test/MC/Mips/mips4/valid.s
@@ -150,10 +150,10 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s
index b444274d78ec7e67bc9c29b45dbc35dd888b924e..cb30de38c295ab23a471aa582a95f43081c4449a 100644 (file)
--- a/test/MC/Mips/mips5/valid.s
+++ b/test/MC/Mips/mips5/valid.s
@@ -151,10 +151,10 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s
index 19ed1ffad1ca4147eaae71dc84f47fd4d1ab8181..58fd8c2063c59894bb3c0399c52dac0e84bc7a06 100644 (file)
--- a/test/MC/Mips/mips64-alu-instructions.s
+++ b/test/MC/Mips/mips64-alu-instructions.s
@@ -84,7 +84,7 @@
 # CHECK:  dsub    $9, $6, $7     # encoding: [0x2e,0x48,0xc7,0x00]
 # CHECK:  dsubu   $4, $3, $5     # encoding: [0x2f,0x20,0x65,0x00]
 # CHECK:  daddiu  $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64]
-# CHECK:  move    $7, $8         # encoding: [0x2d,0x38,0x00,0x01]
+# CHECK:  move    $7, $8         # encoding: [0x25,0x38,0x00,0x01]
 # CHECK:  .set    push
 # CHECK:  .set    mips32r2
 # CHECK:  rdhwr   $5, $29

diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s
index 03ea6c15c333462ddaa6f875ea735781b8301abb..5a557a77e2b2bab8f0e5633813a3dc79e2a5554a 100644 (file)
--- a/test/MC/Mips/mips64/valid.s
+++ b/test/MC/Mips/mips64/valid.s
@@ -163,10 +163,10 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s
index 37753ae0a878fbf65ea995c3a172ae9c61848187..3eb55efbebcd1a7cd80c64facf99763b36ba7119 100644 (file)
--- a/test/MC/Mips/mips64r2/valid.s
+++ b/test/MC/Mips/mips64r2/valid.s
@@ -179,10 +179,10 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips64r3/valid.s b/test/MC/Mips/mips64r3/valid.s
index c5d4848458d2525c5eb6c5e76aefdc6ce6cbcaee..16a85c9376a9e2874e57b3bfa2bd60ecc9a3257f 100644 (file)
--- a/test/MC/Mips/mips64r3/valid.s
+++ b/test/MC/Mips/mips64r3/valid.s
@@ -179,10 +179,10 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips64r5/valid.s b/test/MC/Mips/mips64r5/valid.s
index c570b3e24aac3a2bef6cdeeed77744db8dbed86b..21728735a135c82796814242503d554608be6451 100644 (file)
--- a/test/MC/Mips/mips64r5/valid.s
+++ b/test/MC/Mips/mips64r5/valid.s
@@ -180,10 +180,10 @@ a:
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6

diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s
index 6249d51781c5f285969eebd747b7f6a1bac6be7e..0c6fdbc3802633fa3e5118579f07286b67a7a434 100644 (file)
--- a/test/MC/Mips/mips64r6/valid.s
+++ b/test/MC/Mips/mips64r6/valid.s
@@ -164,6 +164,10 @@ a:
         mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        move    $a0,$a3          # CHECK: move $4, $7             # encoding: [0x00,0xe0,0x20,0x25]
+        move    $s5,$a0          # CHECK: move $21, $4            # encoding: [0x00,0x80,0xa8,0x25]
+        move    $s8,$a0          # CHECK: move $fp, $4            # encoding: [0x00,0x80,0xf0,0x25]
+        move    $25,$a2          # CHECK: move $25, $6            # encoding: [0x00,0xc0,0xc8,0x25]
         mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
         msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]