{
struct dw_spi *dws;
char *buf;
- u32 len = 0;
ssize_t ret;
int reg = 0,value = 0;
/* Return the max entries we can fill into tx fifo */
static inline u32 tx_max(struct dw_spi *dws)
{
- u32 tx_left, tx_room, rxtx_gap;
+ u32 tx_left, tx_room;
tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
tx_room = dws->fifo_len - dw_readw(dws, SPIM_TXFLR);
static int reader_all(struct dw_spi *dws)
{
- u16 rxw;
while (!(dw_readw(dws, SPIM_SR) & SR_RF_EMPT)
&& (dws->rx < dws->rx_end)) {
dw_reader(dws);
u32 speed = 0;
u32 cr0 = 0;
u16 dma_ctrl = 0;
- int ret = 0;
/* Get current state information */
err_queue_alloc:
if (dws->dma_ops && dws->dma_ops->dma_exit)
dws->dma_ops->dma_exit(dws);
-err_diable_hw:
+/* err_diable_hw: */
spi_enable_chip(dws, 0);
free_irq(dws->irq, dws);
err_free_master:
void dw_spi_remove_host(struct dw_spi *dws)
{
- int status = 0;
-
if (!dws)
return;
{
struct spi_dma *dw_dma = dws->dma_priv;
struct spi_dma_slave *rxs, *txs;
- dma_cap_mask_t mask;
DBG_SPI("%s:start\n",__func__);
/* 2. Init tx channel */
dws->txchan = dma_request_slave_channel(dws->parent_dev, "tx");
- if (!dws->rxchan)
+ if (!dws->txchan)
{
- dev_err(dws->parent_dev, "Failed to get RX DMA channel\n");
- goto err_exit;
+ dev_err(dws->parent_dev, "Failed to get TX DMA channel\n");
+ goto free_rxchan;
}
txs = &dw_dma->dmas_tx;
dws->txchan->private = txs;
struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
struct dma_chan *txchan, *rxchan;
struct dma_slave_config txconf, rxconf;
- u16 dma_ctrl = 0;
int ret = 0;
enum dma_slave_buswidth width;
static int rockchip_spi_test_probe(struct spi_device *spi)\r
{ \r
int ret;\r
- int i =0;\r
- char txbuf[256],rxbuf[256]; \r
int id = 0;\r
static struct dw_spi_chip *spi_chip_data;\r
struct spi_test_data *spi_test_data;\r
static int rockchip_spi_probe(struct platform_device *pdev)
{
struct resource *mem_res;
- struct resource *res;
struct rockchip_spi_driver_data *sdd;
struct rockchip_spi_info *info = pdev->dev.platform_data;
struct dw_spi *dws;
- struct spi_master *master;
int ret, irq;
char clk_name[16];