#define TEGRA_RES_SEMA_BASE 0x60001000
#define TEGRA_RES_SEMA_SIZE SZ_4K
+#define TEGRA_ARB_SEMA_BASE 0x60002000
+#define TEGRA_ARB_SEMA_SIZE SZ_4K
+
#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
- #define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
+ #define TEGRA_PRIMARY_ICTLR_SIZE 64
+#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
+#define TEGRA_ARBGNT_ICTLR_SIZE 192
+
#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
- #define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
+ #define TEGRA_SECONDARY_ICTLR_SIZE 64
#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
- #define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
+ #define TEGRA_TERTIARY_ICTLR_SIZE 64
#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
- #define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
+ #define TEGRA_QUATERNARY_ICTLR_SIZE 64
#define TEGRA_TMR1_BASE 0x60005000
#define TEGRA_TMR1_SIZE 8