rockchip: clk: rk3399: make the cpll as parent just for vop

others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.

Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 25c4e1c2ed89ad242fcfdcd0d5330103b477d588..6f14a6f15080275548006e1f193c7f9ed8b35e8a 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -143,6 +143,65 @@ PNAME(mux_ddrclk_p)                                = { "clk_ddrc_lpll_src",
                                                    "clk_ddrc_bpll_src",
                                                    "clk_ddrc_dpll_src",
                                                    "clk_ddrc_gpll_src" };
+
+PNAME(mux_pll_src_vpll_cpll_gpll_p)            = { "vpll", "cpll", "gpll" };
+PNAME(mux_pll_src_dmyvpll_cpll_gpll_p)         = { "dummy_vpll", "cpll", "gpll" };
+
+#ifdef RK3399_TWO_PLL_FOR_VOP
+PNAME(mux_aclk_cci_p)                          = { "dummy_cpll",
+                                                   "gpll_aclk_cci_src",
+                                                   "npll_aclk_cci_src",
+                                                   "vpll_aclk_cci_src" };
+PNAME(mux_cci_trace_p)                         = { "dummy_cpll",
+                                                   "gpll_cci_trace" };
+PNAME(mux_cs_p)                                        = { "dummy_cpll", "gpll_cs",
+                                                   "npll_cs"};
+PNAME(mux_aclk_perihp_p)                       = { "dummy_cpll",
+                                                   "gpll_aclk_perihp_src" };
+
+PNAME(mux_pll_src_cpll_gpll_p)                 = { "dummy_cpll", "gpll" };
+PNAME(mux_pll_src_cpll_gpll_npll_p)            = { "dummy_cpll", "gpll", "npll" };
+PNAME(mux_pll_src_cpll_gpll_ppll_p)            = { "dummy_cpll", "gpll", "ppll" };
+PNAME(mux_pll_src_cpll_gpll_upll_p)            = { "dummy_cpll", "gpll", "upll" };
+PNAME(mux_pll_src_npll_cpll_gpll_p)            = { "npll", "dummy_cpll", "gpll" };
+PNAME(mux_pll_src_cpll_gpll_npll_ppll_p)       = { "dummy_cpll", "gpll", "npll",
+                                                   "ppll" };
+PNAME(mux_pll_src_cpll_gpll_npll_24m_p)                = { "dummy_cpll", "gpll", "npll",
+                                                   "xin24m" };
+PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "dummy_cpll", "gpll", "npll",
+                                                   "clk_usbphy_480m" };
+PNAME(mux_pll_src_ppll_cpll_gpll_npll_p)       = { "ppll", "dummy_cpll", "gpll",
+                                                   "npll", "upll" };
+PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)   = { "dummy_cpll", "gpll", "npll",
+                                                   "upll", "xin24m" };
+PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
+                                                   "ppll", "upll", "xin24m" };
+/*
+ * We hope to be able to HDMI/DP can obtain better signal quality,
+ * therefore, we move VOP pwm and aclk clocks to other PLLs, let
+ * HDMI/DP phyclock can monopolize VPLL.
+ */
+PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p)    = { "dummy_vpll", "dummy_cpll", "gpll",
+                                                   "npll" };
+PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)     = { "dummy_vpll", "dummy_cpll", "gpll",
+                                                   "xin24m" };
+PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
+                                           "dummy_cpll", "gpll" };
+
+PNAME(mux_aclk_emmc_p)                 = { "dummy_cpll",
+                                           "gpll_aclk_emmc_src" };
+
+PNAME(mux_aclk_perilp0_p)              = { "dummy_cpll",
+                                           "gpll_aclk_perilp0_src" };
+
+PNAME(mux_fclk_cm0s_p)                 = { "dummy_cpll",
+                                           "gpll_fclk_cm0s_src" };
+
+PNAME(mux_hclk_perilp1_p)              = { "dummy_cpll",
+                                           "gpll_hclk_perilp1_src" };
+PNAME(mux_aclk_gmac_p)                 = { "dummy_cpll",
+                                           "gpll_aclk_gmac_src" };
+#else
 PNAME(mux_aclk_cci_p)                          = { "cpll_aclk_cci_src",
                                                    "gpll_aclk_cci_src",
                                                    "npll_aclk_cci_src",
@@ -171,9 +230,6 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)        = { "cpll", "gpll", "npll",
                                                    "upll", "xin24m" };
 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
                                                    "ppll", "upll", "xin24m" };
-
-PNAME(mux_pll_src_vpll_cpll_gpll_p)            = { "vpll", "cpll", "gpll" };
-PNAME(mux_pll_src_dmyvpll_cpll_gpll_p)         = { "dummy_vpll", "cpll", "gpll" };
 /*
  * We hope to be able to HDMI/DP can obtain better signal quality,
  * therefore, we move VOP pwm and aclk clocks to other PLLs, let
@@ -183,20 +239,8 @@ PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p)        = { "dummy_vpll", "cpll", "gpll",
                                                    "npll" };
 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)     = { "dummy_vpll", "cpll", "gpll",
                                                    "xin24m" };
-
-PNAME(mux_dclk_vop0_p)                 = { "dclk_vop0_div",
-                                           "dummy_dclk_vop0_frac" };
-PNAME(mux_dclk_vop1_p)                 = { "dclk_vop1_div",
-                                           "dummy_dclk_vop1_frac" };
-
-PNAME(mux_clk_cif_p)                   = { "clk_cifout_src", "xin24m" };
-
-PNAME(mux_pll_src_24m_usbphy480m_p)    = { "xin24m", "clk_usbphy_480m" };
-PNAME(mux_pll_src_24m_pciephy_p)       = { "xin24m", "clk_pciephy_ref100m" };
 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
                                            "cpll", "gpll" };
-PNAME(mux_pciecore_cru_phy_p)          = { "clk_pcie_core_cru",
-                                           "clk_pcie_core_phy" };
 
 PNAME(mux_aclk_emmc_p)                 = { "cpll_aclk_emmc_src",
                                            "gpll_aclk_emmc_src" };
@@ -209,14 +253,26 @@ PNAME(mux_fclk_cm0s_p)                    = { "cpll_fclk_cm0s_src",
 
 PNAME(mux_hclk_perilp1_p)              = { "cpll_hclk_perilp1_src",
                                            "gpll_hclk_perilp1_src" };
+PNAME(mux_aclk_gmac_p)                 = { "cpll_aclk_gmac_src",
+                                           "gpll_aclk_gmac_src" };
+#endif
 
+PNAME(mux_dclk_vop0_p)                 = { "dclk_vop0_div",
+                                           "dummy_dclk_vop0_frac" };
+PNAME(mux_dclk_vop1_p)                 = { "dclk_vop1_div",
+                                           "dummy_dclk_vop1_frac" };
+
+PNAME(mux_clk_cif_p)                   = { "clk_cifout_src", "xin24m" };
+
+PNAME(mux_pll_src_24m_usbphy480m_p)    = { "xin24m", "clk_usbphy_480m" };
+PNAME(mux_pll_src_24m_pciephy_p)       = { "xin24m", "clk_pciephy_ref100m" };
+PNAME(mux_pciecore_cru_phy_p)          = { "clk_pcie_core_cru",
+                                           "clk_pcie_core_phy" };
 PNAME(mux_clk_testout1_p)              = { "clk_testout1_pll_src", "xin24m" };
 PNAME(mux_clk_testout2_p)              = { "clk_testout2_pll_src", "xin24m" };
 
 PNAME(mux_usbphy_480m_p)               = { "clk_usbphy0_480m_src",
                                            "clk_usbphy1_480m_src" };
-PNAME(mux_aclk_gmac_p)                 = { "cpll_aclk_gmac_src",
-                                           "gpll_aclk_gmac_src" };
 PNAME(mux_rmii_p)                      = { "clk_gmac", "clkin_gmac" };
 PNAME(mux_spdif_p)                     = { "clk_spdif_div", "clk_spdif_frac",
                                            "clkin_i2s", "xin12m" };
@@ -607,7 +663,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(5), 9, GFLAGS),
 
        /* spdif */
-       COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(8), 13, GFLAGS),
        COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
@@ -621,7 +677,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 6, GFLAGS),
        /* i2s */
-       COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(8), 3, GFLAGS),
        COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
@@ -631,7 +687,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
                        RK3399_CLKGATE_CON(8), 5, GFLAGS),
 
-       COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(8), 6, GFLAGS),
        COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
@@ -641,7 +697,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
                        RK3399_CLKGATE_CON(8), 8, GFLAGS),
 
-       COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3399_CLKGATE_CON(8), 9, GFLAGS),
        COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
@@ -658,7 +714,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(8), 12, GFLAGS),
 
        /* uart */
-       MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
+       MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
                        RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
        COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
                        RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
@@ -668,7 +724,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(9), 1, GFLAGS,
                        &rk3399_uart0_fracmux),
 
-       MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
+       MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
        COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
                        RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
@@ -694,7 +750,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(9), 7, GFLAGS,
                        &rk3399_uart3_fracmux),
 
-       COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
                        RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
                        RK3399_CLKGATE_CON(3), 4, GFLAGS),
 
@@ -755,7 +811,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(2), 9, GFLAGS),
        GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(2), 10, GFLAGS),
-       COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
+       COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
                        RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
        GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(15), 5, GFLAGS),
@@ -842,7 +898,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(16), 9, GFLAGS),
 
        /* center */
-       COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
                        RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3399_CLKGATE_CON(3), 7, GFLAGS),
        GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
@@ -910,7 +966,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(31), 8, GFLAGS),
 
        /* sdio & sdmmc */
-       COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
                        RK3399_CLKGATE_CON(12), 13, GFLAGS),
        GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
@@ -1189,9 +1245,15 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(28), 0, GFLAGS),
 
+#ifdef RK3399_TWO_PLL_FOR_VOP
+       COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+                       RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
+                       RK3399_CLKGATE_CON(10), 12, GFLAGS),
+#else
        COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 12, GFLAGS),
+#endif
 
        /* The VOP0 is main screen, it is able to re-set parent rate. */
        COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
@@ -1221,9 +1283,15 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(28), 4, GFLAGS),
 
        /* The VOP1 is sub screen, it is note able to re-set parent rate. */
+#ifdef RK3399_TWO_PLL_FOR_VOP
+       COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+                       RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
+                       RK3399_CLKGATE_CON(10), 13, GFLAGS),
+#else
        COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 13, GFLAGS),
+#endif
 
        COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(107), 0,

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index f04bb81a0605c8e80ee5194cade55674b013538c..0fc9e7a00b279643493a3109bc71eb806876d769 100644 (file)
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -16,6 +16,8 @@
 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
 
+/* #define RK3399_TWO_PLL_FOR_VOP */
+
 /* core clocks */
 #define PLL_APLLL                      1
 #define PLL_APLLB                      2
@@ -135,6 +137,12 @@
 #define SCLK_USBPHY1_480M_SRC          169
 #define SCLK_DDRCLK                    170
 #define SCLK_TESTOUT2                  171
+#define SCLK_UART0_SRC                 172
+#define SCLK_UART_SRC                  173
+#define SCLK_I2S0_DIV                  174
+#define SCLK_I2S1_DIV                  175
+#define SCLK_I2S2_DIV                  176
+#define SCLK_SPDIF_DIV                 177
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181