update DPLL rate after change DDR frequency

diff --git a/arch/arm/mach-rk2928/ddr.c b/arch/arm/mach-rk2928/ddr.c
index 9acb76b5c726a2e24a1b021c1fed38144a7519d9..05dbd8f7ce1342bbffa37235321a2f0164ba06a2 100755 (executable)
--- a/arch/arm/mach-rk2928/ddr.c
+++ b/arch/arm/mach-rk2928/ddr.c
@@ -2242,6 +2242,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
                                                                     (ddr_get_cap()>>20));
     ddr_adjust_config(mem_type);
     value=ddr_change_freq(freq);
+    clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
     ddr_print("init success!!! freq=%dMHz\n", value);
 
     calStatusLeft = pPHY_Reg->PHY_REG60;