It turns out that the testcase in question uncovered subreg-handling bug.
authorAnton Korobeynikov <asl@math.spbu.ru>
Sat, 7 Nov 2009 15:20:32 +0000 (15:20 +0000)
committerAnton Korobeynikov <asl@math.spbu.ru>
Sat, 7 Nov 2009 15:20:32 +0000 (15:20 +0000)
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll

index a3f52cdf19d0d4bcf8b5c17e5564d41c2b018262..c130ced62472d019c5bd6d93bcaec2c40aeadb23 100644 (file)
@@ -347,9 +347,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                                &ARM::DPR_VFP2RegClass);
       O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
     } else {
-      if (unsigned SubReg = MO.getSubReg())
-        Reg = TRI->getSubReg(Reg, SubReg);
-
+      assert(!MO.getSubReg() && "Subregs should be eliminated!");
       O << getRegisterName(Reg);
     }
     break;
index 8686961db45ebb15a707b5fe6f9fe8d04d87c5c3..c49fee3a5505ac5ffa83f844c4049d5c53cec049 100644 (file)
@@ -137,6 +137,7 @@ void ARMMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
     case MachineOperand::MO_Register:
       // Ignore all implicit register operands.
       if (MO.isImplicit()) continue;
+      assert(!MO.getSubReg() && "Subregs should be eliminated!");
       MCOp = MCOperand::CreateReg(MO.getReg());
       break;
     case MachineOperand::MO_Immediate:
index 0a06991db2447316810a5678376ad7cad04c1769..fe177c3ea46942ddc467d026914ae3c126433239 100644 (file)
@@ -1,4 +1,5 @@
 ; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
+; XFAIL: *
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "armv7-eabi"