* OK, after changing to use liveIn/liveOut instead of IDEFs,

to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21252 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td
index be2adb347d6b28a39e28f0b2a0b81e42a40f2c81..9d33dc30558203ee4a418cdb969d9df26baabf12 100644 (file)
--- a/lib/Target/IA64/IA64RegisterInfo.td
+++ b/lib/Target/IA64/IA64RegisterInfo.td
@@ -234,7 +234,13 @@ def B6 : GR<0, "b6">;
 // in IA64RegisterInfo.cpp
 
 def GR : RegisterClass<i64, 64, 
-       [r3,  r8,  r9,  r10, r11, r14,
+       [
+       
+//FIXME!: for readability, we don't want the out registers to be the first
+//        ones allocated
+
+        out7, out6, out5, out4, out3, out2, out1, out0,
+        r3,  r8,  r9,  r10, r11, r14,
         r16, r17, r18, r19, r20, r21, r23,
         r24, r25, r26, r27, r28, r29, r30, r31,
         r32, r33, r34, r35, r36, r37, r38, r39,
@@ -249,13 +255,18 @@ def GR : RegisterClass<i64, 64,
         r104, r105, r106, r107, r108, r109, r110, r111,
         r112, r113, r114, r115, r116, r117, r118, r119,
         r120, r121, r122, r123, r124, r125, r126, r127,
-       out0, out1, out2, out3,
-       out4, out5, out6, out7,
-       r0, r1, r2, r12, r13, r15, r22]> // these last 7 are special (look down)
+       r0, r1, r2, r12, r13, r15, r22]> // the last 15 are special (look down)
   {
     let Methods = [{
+
+      iterator allocation_order_begin(MachineFunction &MF) const {
+       // hide registers appropriately:
+       return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
+      }
+
       iterator allocation_order_end(MachineFunction &MF) const {
-       int numReservedRegs=7; // the 15 special registers r0,r1,r2,r12,r13 etc
+       int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
+
        // we also can't allocate registers for use as locals if they're
        // already required as 'out' registers
        numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;

diff --git a/lib/Target/IA64/README b/lib/Target/IA64/README
index ec94299e28f09c42490716c85d09e14f016c5ae6..d1a8fd2fa0fd11651f96e70e0f067b82c34a93da 100644 (file)
--- a/lib/Target/IA64/README
+++ b/lib/Target/IA64/README
@@ -55,6 +55,8 @@ I guarantee it.
 TODO:
 
   - clean up and thoroughly test the isel patterns.
+  - fix stacked register allocation order: (for readability) we don't want
+    the out? registers being the first ones used
   - fix up floating point
     (nb http://gcc.gnu.org/wiki?pagename=ia64%20floating%20point )
   - bundling!