fix macro definition

diff --git a/arch/arm/mach-rk2818/clock.c b/arch/arm/mach-rk2818/clock.c
index d7cd503d821f75232d07797ee6db561692fd9fc0..7435aa9512a7a707a392d269926518613b438c05 100644 (file)
--- a/arch/arm/mach-rk2818/clock.c
+++ b/arch/arm/mach-rk2818/clock.c
@@ -26,6 +26,7 @@
 #include <asm/clkdev.h>
 #include <mach/rk2818_iomap.h>
 #include <mach/scu.h>
+#include <mach/iomux.h>        // CPU_APB_REG0
 
 static struct rockchip_scu_reg_hw
 {
@@ -43,9 +44,9 @@ static struct rockchip_scu_reg_hw
        u32 scu_clksel2_config;
 } *scu_register_base = (struct rockchip_scu_reg_hw *)(RK2818_SCU_BASE);
 
-#define CLKSEL0_REG    (u32 __iomem *)SCU_CLKSEL0_CON
-#define CLKSEL1_REG    (u32 __iomem *)SCU_CLKSEL1_CON
-#define CLKSEL2_REG    (u32 __iomem *)SCU_CLKSEL2_CON
+#define CLKSEL0_REG    (u32 __iomem *)(RK2818_SCU_BASE + SCU_CLKSEL0_CON)
+#define CLKSEL1_REG    (u32 __iomem *)(RK2818_SCU_BASE + SCU_CLKSEL1_CON)
+#define CLKSEL2_REG    (u32 __iomem *)(RK2818_SCU_BASE + SCU_CLKSEL2_CON)
 
 /* SCU PLL CON */
 #define PLL_TEST       (0x01u<<25)
@@ -350,9 +351,9 @@ static int pll_clk_set_rate(struct clk *clk, unsigned long rate)
                writel(v, reg);
 
                /* arm run at 24m */ //FIXME
-               unit = 5600;  /* 24m,0.3ms , 24*300*/
+               unit = 7200;  /* 24m,0.3ms , 24*300*/
                while (unit-- > 0) {
-                       v = readl(RK2818_REGFILE_BASE); //CPU_APB_REG0
+                       v = readl(RK2818_REGFILE_BASE + CPU_APB_REG0);
                        if (v & (0x80u << clk->pll_idx) )
                                break;
                }

diff --git a/arch/arm/mach-rk2818/include/mach/scu.h b/arch/arm/mach-rk2818/include/mach/scu.h
index 65e38e46f9ed09bbbd02e4dffdde1cb24a059716..b2d1c937a880cf61c3c62f3a9249969a4e7f9577 100644 (file)
--- a/arch/arm/mach-rk2818/include/mach/scu.h
+++ b/arch/arm/mach-rk2818/include/mach/scu.h
@@ -86,19 +86,19 @@ enum scu_clk_gate
        CLK_GATE_MAX,
 };
 
-#define SCU_APLL_CON           (RK2818_SCU_BASE + 0x00)
-#define SCU_DPLL_CON           (RK2818_SCU_BASE + 0x04)
-#define SCU_CPLL_CON           (RK2818_SCU_BASE + 0x08)
-#define SCU_MODE_CON           (RK2818_SCU_BASE + 0x0c)
-#define SCU_PMU_CON            (RK2818_SCU_BASE + 0x10)
-#define SCU_CLKSEL0_CON                (RK2818_SCU_BASE + 0x14)
-#define SCU_CLKSEL1_CON                (RK2818_SCU_BASE + 0x18)
-#define SCU_CLKGATE0_CON       (RK2818_SCU_BASE + 0x1c)
-#define SCU_CLKGATE1_CON       (RK2818_SCU_BASE + 0x20)
-#define SCU_CLKGATE2_CON       (RK2818_SCU_BASE + 0x24)
-#define SCU_SOFTRST_CON                (RK2818_SCU_BASE + 0x28)
-#define SCU_CHIPCFG_CON                (RK2818_SCU_BASE + 0x2c)
-#define SCU_CPUPD              (RK2818_SCU_BASE + 0x30)
-#define SCU_CLKSEL2_CON                (RK2818_SCU_BASE + 0x34)
+#define SCU_APLL_CON           0x00
+#define SCU_DPLL_CON           0x04
+#define SCU_CPLL_CON           0x08
+#define SCU_MODE_CON           0x0c
+#define SCU_PMU_CON            0x10
+#define SCU_CLKSEL0_CON                0x14
+#define SCU_CLKSEL1_CON                0x18
+#define SCU_CLKGATE0_CON       0x1c
+#define SCU_CLKGATE1_CON       0x20
+#define SCU_CLKGATE2_CON       0x24
+#define SCU_SOFTRST_CON                0x28
+#define SCU_CHIPCFG_CON                0x2c
+#define SCU_CPUPD              0x30
+#define SCU_CLKSEL2_CON                0x34
 
 #endif