[ARM] tegra: remove inner-writeback memory type from SMP startup

the memory remapping (NMRR) registers were configured differently
by the SMP and LP2 startup code from the standard kernel.

temporarily reverting the inner-writeback change for now.

Change-Id: Ib9c4fc75580d1cc705a5dd83377c0703669bcabc
Signed-off-by: Gary King <gking@nvidia.com>

diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S
index 92851d8a4c46915bd4e4ca9a20b6ae720a6ccd42..7434366aa461444ab2c4041bfb6b7784841ab554 100644 (file)
--- a/arch/arm/mach-tegra/cortex-a9.S
+++ b/arch/arm/mach-tegra/cortex-a9.S
@@ -665,8 +665,8 @@ ENTRY(__return_to_virtual)
        mov     r0, #0x1f
        mcr     p15, 0, r0, c3, c0, 0   @ domain access register
 
-       mov32   r0, 0xff0a89a8
-       mov32   r1, 0x40e044e0
+       mov32   r0, 0xff0a81a8
+       mov32   r1, 0x40e040e0
        mcr     p15, 0, r0, c10, c2, 0  @ PRRR
        mcr     p15, 0, r1, c10, c2, 1  @ NMRR
        mrc     p15, 0, r0, c1, c0, 0