netxen: cache align register map table
authorDhananjay Phadke <dhananjay@netxen.com>
Tue, 7 Apr 2009 22:50:48 +0000 (22:50 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 8 Apr 2009 22:58:31 +0000 (15:58 -0700)
Aligning register offset translation table imporves performance
on rx side.

Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/netxen/netxen_nic_hw.c

index 9439f89869deb75de1ca4307c412fe62f70e8974..3bb2b8c74d92c1d1abf4e2be19fb1ad770a4a026 100644 (file)
@@ -89,7 +89,8 @@ static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
 }
 
 #define CRB_WIN_LOCK_TIMEOUT 100000000
-static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
+static crb_128M_2M_block_map_t
+crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
     {{{0, 0,         0,         0} } },                /* 0: PCI */
     {{{1, 0x0100000, 0x0102000, 0x120000},     /* 1: PCIE */
          {1, 0x0110000, 0x0120000, 0x130000},