#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.9
-# Thu Jun 3 16:12:45 2010
+# Sat Jun 12 13:09:57 2010
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_FW_LOADER=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
#
CONFIG_SND_ROCKCHIP_SOC_I2S=y
CONFIG_SND_ROCKCHIP_SOC_WM8988=y
# CONFIG_SND_ROCKCHIP_SOC_WM8994 is not set
-# CONFIG_SND_ROCKCHIP_SOC_RK1000 is not set
CONFIG_SND_ROCKCHIP_SOC_SLAVE=y
# CONFIG_SND_ROCKCHIP_SOC_MASTER is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_SELECTED=y
#
CONFIG_RK2818_DSP=y
+#
+# RK1000 control
+#
+# CONFIG_RK1000_CONTROL is not set
+
+#
+# rk2818 POWER CONTROL
+#
+CONFIG_RK2818_POWER=y
+
#
# File systems
#
#include <asm/stacktrace.h>
#include <asm/mach/time.h>
+/***************
+* DEBUG
+****************/
+#define RESTART_DEBUG
+#ifdef RESTART_DEBUG
+#define restart_dbg(format, arg...) \
+ printk("RESTART_DEBUG : " format "\n" , ## arg)
+#else
+#define restart_dbg(format, arg...) do {} while (0)
+#endif
+
+
static const char *processor_modes[] = {
"USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
"UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
void arm_machine_restart(char mode, const char *cmd)
{
+ /*
+ * debug trace
+ */
+ restart_dbg("%s->%s->%d->mode=%d cmd=%s",__FILE__,__FUNCTION__,__LINE__,mode,cmd);
/*
* Clean and disable cache, and turn off interrupts
*/
void machine_power_off(void)
{
+ restart_dbg("%s->%s->%d",__FILE__,__FUNCTION__,__LINE__);
if (pm_power_off)
pm_power_off();
}
void machine_restart(char *cmd)
{
+ restart_dbg("%s->%s->%d->cmd=%s reboot_mode=%c",__FILE__,__FUNCTION__,__LINE__,cmd,reboot_mode);
+ if(reboot_mode == 'h') /*no boot parameter*/
+ reboot_mode = 0;
+ if(cmd) {
+ reboot_mode = 0;
+ if( !strcmp( cmd , "recovery" ) )
+ reboot_mode = 3;
+ else if( !strcmp( cmd , "loader" ) )
+ reboot_mode = 1;
+ }
arm_pm_restart(reboot_mode, cmd);
}
#include <linux/irqflags.h>
#include <linux/string.h>
#include <linux/version.h>
-
+#include <asm/uaccess.h>
#include <asm/tcm.h>
+#include <asm/io.h>
+
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
#include <mach/rk2818_iomap.h>
#include <mach/memory.h>
uint32 __tcmdata DDRnewKHz = 400000 ; //266000;
uint32 __tcmdata SDRAMoldKHz = 66000;
uint32 __tcmdata DDRoldKHz = 200000;
- unsigned int __tcmdata ddr_reg[8] ;
- volatile int __tcmdata rk28_debugs = 0;
+
+ volatile int __tcmdata rk28_debugs = 1;
uint32 __tcmdata save_sp;
__tcmdata uint32 bFreqRaise;
uint32 memType = DDR_MEM_TYPE();// (pGRF_Reg->CPU_APB_REG0) & MEMTYPEMASK;
uint32 tmp;
volatile uint32 *p_ddr = (volatile uint32 *)0xc0080000;
- //uint32 *ddr_reg = 0xff401c00;
- ddr_reg[0] = pGRF_Reg->CPU_APB_REG0;
- ddr_reg[1] = pGRF_Reg->CPU_APB_REG1;
-
-
- ddr_reg[4] = pDDR_Reg->CTRL_REG_10;
-
- ddr_reg[6] = pDDR_Reg->CTRL_REG_78;
+
+
switch(memType)
{
case Mobile_SDRAM:
}
DDRPreUpdateRef(DDRnewKHz);
DDRPreUpdateTiming(DDRnewKHz);
- printk("%s::just befor ddr refresh.ahb=%ld,new ddr=%ld\n" , __func__ , SDRAMnewKHz , DDRnewKHz);
+ printk("%s::just befor ddr refresh.ahb=%ld,new ddr=%ld\n" , __func__ , SDRAMnewKHz , DDRnewKHz);
//WAIT_ME();
while(pGRF_Reg->CPU_APB_REG1 & 0x100);
tmp = *p_ddr; //read to wakeup
uint32 ddrKHz;
//uint32 ahbKHz;
uint32 memType = DDR_MEM_TYPE();// (pGRF_Reg->CPU_APB_REG0) & MEMTYPEMASK;
- DDR_debug_string("21\n");
switch(memType)
{
case Mobile_SDRAM:
}
pDDR_Reg->CTRL_REG_09 &= ~(0x1 << 24);
while(pDDR_Reg->CTRL_REG_03 & 0x100); // exit
- printk("exit ddr refresh,");
+ //printk("exit ddr refresh,");
//Í˳ö×Ôˢкó£¬ÔÙËãelementµÄÖµ
ddrKHz = PLLGetDDRFreq();
- printk("new ddr kHz=%ld\n" , ddrKHz);
+ //printk("new ddr kHz=%ld\n" , ddrKHz);
if(110000 < ddrKHz)
{
value = pDDR_Reg->CTRL_REG_78;
}
}
-static void __tcmfunc rk281x_restart( void )
-{
- void (*boot)(void) = (void (*)(void))0;
- #define pSCU_Reg ((pSCU_REG)SCU_BASE_ADDR_VA)
- #define pGRF_Reg ((pGRF_REG)REG_FILE_BASE_ADDR_VA)
-
- asm( "MRC p15,0,r0,c1,c0,0\n"
- "BIC r0,r0,#(1<<0) @disable mmu\n"
- "BIC r0,r0,#(1<<13) @set vector to 0x00000000\n"
- "MCR p15,0,r0,c1,c0,0\n"
- "mov r1,r1\n"
- "mov r1,r1\n" );
- pSCU_Reg->SCU_MODE_CON |= (3<<2); // arm slow mod
- pGRF_Reg->CPU_APB_REG5 &= ~(1<<0); // no remap.
- boot();
-}
/*SCU PLL CON , 20100518,copy from rk28_scu_hw.c
pDDR_Reg->CTRL_REG_36 = 0x1F1F;
printk("..%s -->capability ==%ld telement==%ld -->%d\n",__FUNCTION__,capability,telement,__LINE__);
- ddr_change_freq( 351 );
+ ddr_change_freq( 266 );
}
+
unsigned long ddr_save_sp( unsigned long new_sp );
asm(
" .section \".tcm.text\",\"ax\"\n"
" .previous"
);
-void(*rk28_restart_mmu)(void )= (void(*)(void ))rk281x_restart;
+
extern void clk_recalculate_root_clocks(void);
unsigned long ps_sram = (DTCM_END&(~7));
//printk(">>>>>%s-->%d\n",__FUNCTION__,__LINE__);
int *reg = (int *)(SCU_BASE_ADDR_VA);
- ddr_reg[0] = pGRF_Reg->CPU_APB_REG0;
- ddr_reg[1] = pGRF_Reg->CPU_APB_REG1;
- ddr_reg[2] = pDDR_Reg->CTRL_REG_03;
- ddr_reg[3] = pDDR_Reg->CTRL_REG_09;
- ddr_reg[4] = pDDR_Reg->CTRL_REG_10;
- ddr_reg[5] = pDDR_Reg->CTRL_REG_36;
- ddr_reg[6] = pDDR_Reg->CTRL_REG_78;
- printk(" before 0x%08x 0x%08x 0x%08x 0x%08x\n"
- "0x%08x 0x%08x 0x%08x \n"
- // "0x%08x 0x%08x 0x%08x 0x%08x\n" ,
- ,ddr_reg[0],ddr_reg[1],ddr_reg[2],ddr_reg[3],
- ddr_reg[4],ddr_reg[5],ddr_reg[6]);
+
strcpy( (char*)(ps_sram-0x40) , "rk281x_ddr_sram-wqq\n" );
// printk( "sram data:%s\n" , (char*)(ps_sram-0x40) );
local_irq_disable();
SDRAM_DDR_Init();
ddr_save_sp(save_sp);
printk("after SDRAM_DDR_Init\n");
- local_irq_enable();
- ddr_reg[0] = pGRF_Reg->CPU_APB_REG0;
- ddr_reg[1] = pGRF_Reg->CPU_APB_REG1;
- ddr_reg[2] = pDDR_Reg->CTRL_REG_03;
- ddr_reg[3] = pDDR_Reg->CTRL_REG_09;
- ddr_reg[4] = pDDR_Reg->CTRL_REG_10;
- ddr_reg[5] = pDDR_Reg->CTRL_REG_36;
- ddr_reg[6] = pDDR_Reg->CTRL_REG_78;
- printk("after 0x%08x 0x%08x 0x%08x 0x%08x\n"
- "0x%08x 0x%08x 0x%08x \n"
- // "0x%08x 0x%08x 0x%08x 0x%08x\n" ,
- ,ddr_reg[0],ddr_reg[1],ddr_reg[2],ddr_reg[3],
- ddr_reg[4],ddr_reg[5],ddr_reg[6]);
+ local_irq_enable();
printk("scu after frq%s::\n0x%08x 0x%08x 0x%08x 0x%08x\n"
"0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n"
}
core_initcall_sync(update_frq);
+/****************************************************************/
+//º¯ÊýÃû:SDRAM_DDR_Disable_Sleep
+//ÃèÊö:½ûÖ¹×Ô¶¯sleepģʽ
+//²ÎÊý˵Ã÷:
+//·µ»ØÖµ:
+//Ïà¹ØÈ«¾Ö±äÁ¿:
+//×¢Òâ:
+/****************************************************************/
+static void SDRAM_DDR_Disable_Sleep(void)
+{
+ volatile uint32 *p_ddr = (volatile uint32 *)0xc0080000;
+ unsigned int tmp;
+ while(pGRF_Reg->CPU_APB_REG1 & 0x100);
+ tmp = *p_ddr; //read to wakeup
+ pDDR_Reg->CTRL_REG_36 &= ~(0x1F << 8);
+ while(pDDR_Reg->CTRL_REG_03 & 0x100)
+ {
+ tmp = *p_ddr; //read to wakeup
+ }
+ while(pGRF_Reg->CPU_APB_REG1 & 0x100);
+}
+
+static void rk2818_reduce_ddrfrq(void)
+{
+ unsigned long ps_sram = (DTCM_END&(~7));
+ save_sp = ddr_save_sp(ps_sram);
+ ddr_change_freq( 133);
+ ddr_save_sp(save_sp);
+}
+static void __tcmfunc rk2818_reduce_corevoltage(int mmu)
+{
+#define read_XDATA32(address) (*((unsigned int volatile*)(address)))
+#define write_XDATA32(address, value) (*((unsigned int volatile*)(address)) = value)
+
+ if(mmu)
+ {
+
+ write_XDATA32((RK2818_GPIO1_BASE+0x24), (read_XDATA32(RK2818_GPIO1_BASE+0x24)&(~(1ul<<6)))); //GPIOPortH_Pin6
+ write_XDATA32((RK2818_GPIO1_BASE+0x28), (read_XDATA32(RK2818_GPIO1_BASE+0x28)&(~(1ul<<6))));
+ }
+ else
+ {
+ write_XDATA32((RK2818_GPIO1_PHYS+0x24), 0);//GPIOPortH_Pin6
+ write_XDATA32((RK2818_GPIO1_PHYS+0x28), 0);
+ }
+}
+ void __tcmfunc rk281x_restart( void )
+{
+ int i;
+ void (*boot)(void) = (void (*)(void))0;
+ #define pSCU_Reg ((pSCU_REG)SCU_BASE_ADDR_VA)
+ #define pGRF_Reg ((pGRF_REG)REG_FILE_BASE_ADDR_VA)
+ SDRAM_DDR_Disable_Sleep();
+ pSCU_Reg->SCU_CLKSEL0_CON &= (~(3<<2));
+ pSCU_Reg->SCU_MODE_CON |= (3<<2); // arm slow mod
+ for(i=0;i<10000;i++);
+ pGRF_Reg->CPU_APB_REG5 &= ~(1<<0); // no remap.
+
+ rk2818_reduce_corevoltage(1);
+ asm( "MRC p15,0,r0,c1,c0,0\n"
+ "BIC r0,r0,#(1<<0) @disable mmu\n"
+ "BIC r0,r0,#(1<<13) @set vector to 0x00000000\n"
+ "MCR p15,0,r0,c1,c0,0\n"
+ "mov r1,r1\n"
+ "mov r1,r1\n"
+ "ldr r2,=0x10040804 @usb soft disconnect.\n"
+ " mov r3,#2\n"
+ "str r3,[r2,#0]\n"
+
+ "ldr r2,=0x100AE00C @ BCH reset.\n"
+ " mov r3,#1\n"
+ "str r3,[r2,#0]\n"
+ );
+ //while(rk28_debugs);
+ boot();
+}
+
+
+void(*rk2818_reboot)(void )= (void(*)(void ))rk281x_restart;
+
#if 0
/****************************************************************/
//º¯ÊýÃû:SDRAM_EnterSelfRefresh
--- /dev/null
+/*
+* Copyright (C) 2010 ROCKCHIP, Inc.
+*
+* This software is licensed under the terms of the GNU General Public
+* License version 2, as published by the Free Software Foundation, and
+* may be copied, distributed, and modified under those terms.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+*/
+
+#include <linux/irqflags.h>
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include <mach/gpio.h>
+#include <mach/hardware.h>
+#include <mach/rk2818_iomap.h>
+
+/***************
+* DEBUG
+****************/
+#define RESTART_DEBUG
+#ifdef RESTART_DEBUG
+#define restart_dbg(format, arg...) \
+ printk("RESTART_DEBUG : " format "\n" , ## arg)
+#else
+#define restart_dbg(format, arg...) do {} while (0)
+#endif
+
+extern void(*rk2818_reboot)(void );
+
+static void rk2818_kernel_reboot(void)
+{
+ restart_dbg("%s->%s->%d",__FILE__,__FUNCTION__,__LINE__);
+ local_irq_disable();
+ rk2818_reboot();
+}
+
+
+/*
+ * reset: 0 : normal reset 1: panic , 2: hard reset.
+ * boot : 0: normal , 1: loader , 2: maskrom , 3:recovery
+ *
+ */
+
+ int rk2818_restart( int mode, const char *cmd)
+{
+ restart_dbg("%s->%s->%d",__FILE__,__FUNCTION__,__LINE__);
+ switch ( mode ) {
+ case 0:
+ rk2818_kernel_reboot( ); // normal
+ break;
+ case 1:
+ //rk28_usb();
+ //kld_reboot( 0 , type ); // loader usb
+ break;
+ case 2:
+ //rk28_usb();
+ //kld_reboot( 0 , type ); // maksrom usb
+ break;
+ case 3:
+ //kld_reboot( 0 , type ); // normal and recover
+ break;
+ case 4:
+ *(int*)(0xfe04c0fa) = 0xe5e6e700;
+ break;
+ default:
+ {
+ void(*deader)(void) = (void(*)(void))0xc600c400;
+ deader();
+ }
+ break;
+ }
+ return 0x24;
+}
+EXPORT_SYMBOL(rk2818_restart);
+