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[X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. There...
author
Craig Topper
<craig.topper@gmail.com>
Wed, 7 Jan 2015 08:10:36 +0000
(08:10 +0000)
committer
Craig Topper
<craig.topper@gmail.com>
Wed, 7 Jan 2015 08:10:36 +0000
(08:10 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225344
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/X86/X86InstrShiftRotate.td
patch
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diff --git
a/lib/Target/X86/X86InstrShiftRotate.td
b/lib/Target/X86/X86InstrShiftRotate.td
index 3f1646907b6f3bedb9a74aaba00132f849c015fb..c706d43c9f5c65d17a9468f6e546e6bfde43cd0a 100644
(file)
--- a/
lib/Target/X86/X86InstrShiftRotate.td
+++ b/
lib/Target/X86/X86InstrShiftRotate.td
@@
-49,6
+49,7
@@
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
"shl{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
IIC_SR>;
+} // isConvertibleToThreeAddress = 1
// NOTE: We don't include patterns for shifts of a register by one, because
// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
@@
-62,7
+63,6
@@
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
"shl{q}\t$dst", [], IIC_SR>;
} // hasSideEffects = 0
-} // isConvertibleToThreeAddress = 1
} // Constraints = "$src = $dst", SchedRW