phy: rockchip-inno-usb2: add host-port support for rk322x SoC

This adds support host-port on rk322x SoC and amend phy Documentation.

Change-Id: I440adc10e25c98cbe220275fecd12774c08d24d1
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
index 6e3147d866de466247d04e5cc61172d0c00a9f77..121c521a4313101e8105b038fa43454990301d83 100644 (file)
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
@@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
 
 Required properties (phy (parent) node):
  - compatible : should be one of the listed compatibles:
+       * "rockchip,rk322x-usb2phy"
        * "rockchip,rk3328-usb2phy"
        * "rockchip,rk3366-usb2phy"
        * "rockchip,rk3368-usb2phy"

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index 3afda20675b5a238711b756efbd13164c0697873..6dc05d956910cc0815a5dda2d0b79efca89278b1 100644 (file)
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -1541,6 +1541,36 @@ static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
 #define ROCKCHIP_USB2PHY_DEV_PM        NULL
 #endif /* CONFIG_PM_SLEEP */
 
+static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
+       {
+               .reg = 0x760,
+               .num_ports      = 2,
+               .clkout_ctl     = { 0x0768, 4, 4, 1, 0 },
+               .port_cfgs      = {
+                       [USB2PHY_PORT_HOST] = {
+                               .phy_sus        = { 0x0764, 15, 0, 0, 0x1d1 },
+                               .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
+                               .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
+                               .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 }
+                       }
+               },
+       },
+       {
+               .reg = 0x800,
+               .num_ports      = 2,
+               .clkout_ctl     = { 0x0808, 4, 4, 1, 0 },
+               .port_cfgs      = {
+                       [USB2PHY_PORT_HOST] = {
+                               .phy_sus        = { 0x800, 15, 0, 0, 0x1d1 },
+                               .ls_det_en      = { 0x0684, 0, 0, 0, 1 },
+                               .ls_det_st      = { 0x0694, 0, 0, 0, 1 },
+                               .ls_det_clr     = { 0x06a4, 0, 0, 0, 1 }
+                       }
+               },
+       },
+       { /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
        {
                .reg = 0x100,
@@ -1718,6 +1748,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
 };
 
 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
+       { .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
        { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
        { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
        { .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs },