The PPC64 ELF ABI is "intended to use the same structure layout and calling conventio...

as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td
index b75ec40f6f45ee7514c9c0363b00e8549e84d7b5..9e31b5a6690c8af06a3bb87970b3466dbefbdd77 100644 (file)
--- a/lib/Target/PowerPC/PPCCallingConv.td
+++ b/lib/Target/PowerPC/PPCCallingConv.td
@@ -41,10 +41,10 @@ def CC_PPC : CallingConv<[
   CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
   CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
   
-  // Darwin passes FP values in F1 - F13
+  // Common sub-targets passes FP values in F1 - F13
   CCIfType<[f32, f64], CCIfSubtarget<"isMachoABI()",
            CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>>,
-  // Other sub-targets pass FP values in F1-F8.
+  // ELF32 sub-target pass FP values in F1 - F8.
   CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
            
   // The first 12 Vector arguments are passed in altivec registers.

diff --git a/lib/Target/PowerPC/PPCFrameInfo.h b/lib/Target/PowerPC/PPCFrameInfo.h
index 0c728247301e2ab002e6f1a9f3d7058f3738730f..535e82386d053517b974d829862bfc6081c2ec0d 100644 (file)
--- a/lib/Target/PowerPC/PPCFrameInfo.h
+++ b/lib/Target/PowerPC/PPCFrameInfo.h
@@ -32,8 +32,8 @@ public:
   static unsigned getReturnSaveOffset(bool LP64, bool isMacho) {
     if (isMacho)
       return LP64 ? 16 : 8;
-    // For ELF ABI:
-    return LP64 ? 8 : 4;
+    // For ELF 32 ABI:
+    return 4;
   }
 
   /// getFramePointerSaveOffset - Return the previous frame offset to save the
@@ -46,9 +46,9 @@ public:
     if (isMacho)
       return LP64 ? 40 : 20;
     
-    // For ELF ABI:
+    // For ELF 32 ABI:
     // Save it right before the link register
-    return LP64 ? -8 : -4;
+    return -4;
   }
   
   /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
@@ -57,8 +57,8 @@ public:
     if (isMacho)
       return 6 * (LP64 ? 8 : 4);
     
-    // For ELF ABI:
-    return LP64 ? 16 : 8;
+    // For ELF 32 ABI:
+    return 8;
   }
 
   /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
@@ -73,7 +73,7 @@ public:
     if (isMacho)
       return 8 * (LP64 ? 8 : 4);
     
-    // For Linux ABI:
+    // For ELF 32 ABI:
     // There is no default stack allocated for the 8 first GPR arguments.
     return 0;
   }

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 5ac87104f99a9b5ee6c16e9847de47842d50686e..5efeaf4c19fcb60169f7b08db4ebd848b2f14406 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1132,7 +1132,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
   MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
   bool isPPC64 = PtrVT == MVT::i64;
   bool isMachoABI = Subtarget.isMachoABI();
-  bool isELF_ABI = Subtarget.isELF_ABI();
+  bool isELF32_ABI = Subtarget.isELF32_ABI();
   unsigned PtrByteSize = isPPC64 ? 8 : 4;
 
   unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
@@ -1165,7 +1165,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
   // entry to a function on PPC, the arguments start after the linkage area,
   // although the first ones are often in registers.
   // 
-  // In the ELF ABI, GPRs and stack are double word align: an argument
+  // In the ELF 32 ABI, GPRs and stack are double word align: an argument
   // represented with two words (long long or double) must be copied to an
   // even GPR_idx value or to an even ArgOffset value.
 
@@ -1187,7 +1187,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
     default: assert(0 && "Unhandled argument type!");
     case MVT::i32:
       // Double word align in ELF
-      if (Expand && isELF_ABI && !isPPC64) GPR_idx += (GPR_idx % 2);
+      if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
       if (GPR_idx != Num_GPR_Regs) {
         unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
         MF.addLiveIn(GPR[GPR_idx], VReg);
@@ -1198,7 +1198,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
         ArgSize = PtrByteSize;
       }
       // Stack align in ELF
-      if (needsLoad && Expand && isELF_ABI && !isPPC64) 
+      if (needsLoad && Expand && isELF32_ABI) 
         ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
       // All int arguments reserve stack space in Macho ABI.
       if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
@@ -1240,7 +1240,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
       }
       
       // Stack align in ELF
-      if (needsLoad && Expand && isELF_ABI && !isPPC64)
+      if (needsLoad && Expand && isELF32_ABI)
         ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
       // All FP arguments reserve stack space in Macho ABI.
       if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
@@ -1344,7 +1344,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
   unsigned NumOps  = (Op.getNumOperands() - 5) / 2;
   
   bool isMachoABI = Subtarget.isMachoABI();
-  bool isELF_ABI  = Subtarget.isELF_ABI();
+  bool isELF32_ABI  = Subtarget.isELF32_ABI();
 
   MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
   bool isPPC64 = PtrVT == MVT::i64;
@@ -1432,8 +1432,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
     // register cannot be found for it.
     SDOperand PtrOff;
     
-    // Stack align in ELF
-    if (isELF_ABI && Expand && !isPPC64)
+    // Stack align in ELF 32
+    if (isELF32_ABI && Expand)
       PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
                                StackPtr.getValueType());
     else
@@ -1453,7 +1453,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
     case MVT::i32:
     case MVT::i64:
       // Double word align in ELF
-      if (isELF_ABI && Expand && !isPPC64) GPR_idx += (GPR_idx % 2);
+      if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
       if (GPR_idx != NumGPRs) {
         RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
       } else {
@@ -1462,7 +1462,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
       }
       if (inMem || isMachoABI) {
         // Stack align in ELF
-        if (isELF_ABI && Expand && !isPPC64)
+        if (isELF32_ABI && Expand)
           ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
 
         ArgOffset += PtrByteSize;
@@ -1516,7 +1516,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
       }
       if (inMem || isMachoABI) {
         // Stack align in ELF
-        if (isELF_ABI && Expand && !isPPC64)
+        if (isELF32_ABI && Expand)
           ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
         if (isPPC64)
           ArgOffset += 8;
@@ -1548,8 +1548,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
     InFlag = Chain.getValue(1);
   }
  
-  // With the ELF ABI, set CR6 to true if this is a vararg call.
-  if (isVarArg && isELF_ABI) {
+  // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
+  if (isVarArg && isELF32_ABI) {
     SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
     Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
     InFlag = Chain.getValue(1);

diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index e6ede49fbeeb9239679d3a1627bdac727f330a03..e82a376afaeb28b8f08b1b364d3c0cfe89d22411 100644 (file)
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -87,11 +87,12 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7,
                          "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
 }
 
-// ELF ABI Calls.
+// ELF 64 ABI Calls = Macho ABI Calls
+// Used to define BL8_ELF and BLA8_ELF
 let isCall = 1, noResults = 1, PPC970_Unit = 7, 
   // All calls clobber the PPC64 non-callee saved registers.
   Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
-          F0,F1,F2,F3,F4,F5,F6,F7,F8,
+          F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
           V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
           LR8,CTR8,
           CR0,CR1,CR5,CR6,CR7] in {

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 095eab4217be85aed822656526a1c0ec88b3aa79..dbf2cf48b153b1d839815d603ee54c00dfce8ec8 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -250,7 +250,7 @@ void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
 
 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
   // 32-bit Darwin calling convention. 
-  static const unsigned Darwin32_CalleeSavedRegs[] = {
+  static const unsigned Macho32_CalleeSavedRegs[] = {
               PPC::R13, PPC::R14, PPC::R15,
     PPC::R16, PPC::R17, PPC::R18, PPC::R19,
     PPC::R20, PPC::R21, PPC::R22, PPC::R23,
@@ -294,7 +294,7 @@ const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
     PPC::LR,  0
   };
   // 64-bit Darwin calling convention. 
-  static const unsigned Darwin64_CalleeSavedRegs[] = {
+  static const unsigned Macho64_CalleeSavedRegs[] = {
     PPC::X14, PPC::X15,
     PPC::X16, PPC::X17, PPC::X18, PPC::X19,
     PPC::X20, PPC::X21, PPC::X22, PPC::X23,
@@ -315,41 +315,18 @@ const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
     PPC::LR8,  0
   };
   
-  static const unsigned ELF64_CalleeSavedRegs[] = {
-    PPC::X14, PPC::X15,
-    PPC::X16, PPC::X17, PPC::X18, PPC::X19,
-    PPC::X20, PPC::X21, PPC::X22, PPC::X23,
-    PPC::X24, PPC::X25, PPC::X26, PPC::X27,
-    PPC::X28, PPC::X29, PPC::X30, PPC::X31,
-                                  
-                                  PPC::F9,
-    PPC::F10, PPC::F11, PPC::F12, PPC::F13,
-    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
-    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
-    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
-    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
-    PPC::F30, PPC::F31,
-    
-    PPC::CR2, PPC::CR3, PPC::CR4,
-    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
-    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
-    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
-    
-    PPC::LR8,  0
-  };
-  
   if (Subtarget.isMachoABI())
-    return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
-                                 Darwin32_CalleeSavedRegs;
+    return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
+                                 Macho32_CalleeSavedRegs;
   
-  // ELF.
-  return Subtarget.isPPC64() ? ELF64_CalleeSavedRegs : ELF32_CalleeSavedRegs;
+  // ELF 32.
+  return ELF32_CalleeSavedRegs;
 }
 
 const TargetRegisterClass* const*
 PPCRegisterInfo::getCalleeSavedRegClasses() const {
-  // 32-bit Darwin calling convention. 
-  static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
+  // 32-bit Macho calling convention. 
+  static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
                        &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
@@ -395,8 +372,8 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const {
     &PPC::GPRCRegClass, 0
   };
   
-  // 64-bit Darwin calling convention. 
-  static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
+  // 64-bit Macho calling convention. 
+  static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
     &PPC::G8RCRegClass,&PPC::G8RCRegClass,
     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
@@ -418,37 +395,12 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const {
     &PPC::G8RCRegClass, 0
   };
   
-  static const TargetRegisterClass * const ELF64_CalleeSavedRegClasses[] = {
-    &PPC::G8RCRegClass,&PPC::G8RCRegClass,
-    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
-    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
-    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
-    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
-    
-                                                             &PPC::F8RCRegClass,
-    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
-    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
-    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
-    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
-    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
-    &PPC::F8RCRegClass,&PPC::F8RCRegClass,
-    
-    &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
-    
-    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
-    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
-    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
-    
-    &PPC::G8RCRegClass, 0
-  };
- 
   if (Subtarget.isMachoABI())
-    return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
-                                 Darwin32_CalleeSavedRegClasses;
+    return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
+                                 Macho32_CalleeSavedRegClasses;
   
-  // ELF.
-  return Subtarget.isPPC64() ? ELF64_CalleeSavedRegClasses :
-                               ELF32_CalleeSavedRegClasses;
+  // ELF 32.
+  return ELF32_CalleeSavedRegClasses;
 }
 
 // needsFP - Return true if the specified function should have a dedicated frame
@@ -900,15 +852,16 @@ void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
   //  Save R31 if necessary
   int FPSI = FI->getFramePointerSaveIndex();
   bool IsPPC64 = Subtarget.isPPC64();
-  bool IsELF_ABI = Subtarget.isELF_ABI();
+  bool IsELF32_ABI = Subtarget.isELF32_ABI();
+  bool IsMachoABI  = Subtarget.isMachoABI();
   const MachineFrameInfo *MFI = MF.getFrameInfo();
  
   // If the frame pointer save index hasn't been defined yet.
   if (!FPSI &&  (NoFramePointerElim || MFI->hasVarSizedObjects()) 
-                                                  && IsELF_ABI) {
+                                                  && IsELF32_ABI) {
     // Find out what the fix offset of the frame pointer save area.
-    int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 
-                                                              !IsELF_ABI);
+    int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
+                                                           IsMachoABI);
     // Allocate the frame index for frame pointer save area.
     FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
     // Save the result.

diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h
index eedcf3cb11e9559dec44722e91aae2e83a182c9a..d1e135c32f553193c023ad777c6eb3ceefef639a 100644 (file)
--- a/lib/Target/PowerPC/PPCSubtarget.h
+++ b/lib/Target/PowerPC/PPCSubtarget.h
@@ -134,8 +134,8 @@ public:
 
   bool isDarwin() const { return IsDarwin; }
 
-  bool isMachoABI() const { return IsDarwin; }
-  bool isELF_ABI() const { return !IsDarwin; }
+  bool isMachoABI() const { return IsDarwin || IsPPC64; }
+  bool isELF32_ABI() const { return !IsDarwin && !IsPPC64; }
 
   unsigned getAsmFlavor() const {
     return AsmFlavor != Unset ? unsigned(AsmFlavor) : 0;