#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pinctrl/rockchip-rk3188.h>
#include "skeleton.dtsi"
};
pinctrl@20008000 {
- compatible = "rockchip,rk3188-pinctrl";
- reg = <0x20008000 0xa0>,
- <0x20008164 0x1a0>;
- reg-names = "base", "pull";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ compatible = "rockchip,rk3188-pinctrl";
+ reg = <0x20008000 0xa0>,
+ <0x20008164 0x1a0>;
+ reg-names = "base", "pull";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- gpio0: gpio0@0x2000a000 {
- compatible = "rockchip,rk3188-gpio-bank0";
- reg = <0x2000a000 0x100>,
- <0x20004064 0x8>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- /*clocks = <&clk_gates8 9>;*/
+ gpio0: gpio0@0x2000a000 {
+ compatible = "rockchip,rk3188-gpio-bank0";
+ reg = <0x2000a000 0x100>,
+ <0x20004064 0x8>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ /*clocks = <&clk_gates8 9>;*/
- gpio-controller;
- #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- gpio1: gpio1@0x2003c000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x2003c000 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- /*clocks = <&clk_gates8 10>;*/
+ gpio1: gpio1@0x2003c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2003c000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ /*clocks = <&clk_gates8 10>;*/
- gpio-controller;
- #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- gpio2: gpio2@2003e000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x2003e000 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- /*clocks = <&clk_gates8 11>;*/
+ gpio2: gpio2@2003e000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2003e000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ /*clocks = <&clk_gates8 11>;*/
- gpio-controller;
- #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio3@20080000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x20080000 0x100>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- /*clocks = <&clk_gates8 12>;*/
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- gpio-controller;
- #gpio-cells = <2>;
+ gpio3: gpio3@20080000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ /*clocks = <&clk_gates8 12>;*/
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ gpio-controller;
+ #gpio-cells = <2>;
- pcfg_pull_up: pcfg_pull_up {
- bias-pull-up;
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- pcfg_pull_down: pcfg_pull_down {
- bias-pull-down;
- };
+ pcfg_pull_up: pcfg_pull_up {
+ bias-pull-up;
+ };
- pcfg_pull_none: pcfg_pull_none {
- bias-disable;
- };
+ pcfg_pull_down: pcfg_pull_down {
+ bias-pull-down;
+ };
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
- };
+ pcfg_pull_none: pcfg_pull_none {
+ bias-disable;
+ };
- uart0_cts: uart0-cts {
- rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <UART0_SIN &pcfg_pull_none>,
+ <UART0_SOUT &pcfg_pull_none>;
+ };
- uart0_rts: uart0-rts {
- rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart0_cts: uart0-cts {
+ rockchip,pins = <UART0_CTSN &pcfg_pull_none>;
};
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart0_rts: uart0-rts {
+ rockchip,pins = <UART0_RTSN &pcfg_pull_none>;
+ };
+ };
- uart1_cts: uart1-cts {
- rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <UART1_SIN &pcfg_pull_none>,
+ <UART1_SOUT &pcfg_pull_none>;
+ };
- uart1_rts: uart1-rts {
- rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart1_cts: uart1-cts {
+ rockchip,pins = <UART1_CTSN &pcfg_pull_none>;
};
- uart2 {
- uart2_xfer: uart2-xfer {
- rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
- };
- /* no rts / cts for uart2 */
+ uart1_rts: uart1-rts {
+ rockchip,pins = <UART1_RTSN &pcfg_pull_none>;
};
+ };
- uart3 {
- uart3_xfer: uart3-xfer {
- rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <UART2_SIN &pcfg_pull_none>,
+ <UART2_SOUT &pcfg_pull_none>;
+ };
+ /* no rts / cts for uart2 */
+ };
- uart3_cts: uart3-cts {
- rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart3 {
+ uart3_xfer: uart3-xfer {
+ rockchip,pins = <UART3_SIN &pcfg_pull_none>,
+ <UART3_SOUT &pcfg_pull_none>;
+ };
- uart3_rts: uart3-rts {
- rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart3_cts: uart3-cts {
+ rockchip,pins = <UART3_CTSN &pcfg_pull_none>;
};
- sd0 {
- sd0_clk: sd0-clk {
- rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
- };
+ uart3_rts: uart3-rts {
+ rockchip,pins = <UART3_RTSN &pcfg_pull_none>;
+ };
+ };
+
+ sd0 {
+ sd0_clk: sd0-clk {
+ rockchip,pins = <MMC0_CLKOUT &pcfg_pull_none>;
+ };
- sd0_cmd: sd0-cmd {
- rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd0_cmd: sd0-cmd {
+ rockchip,pins = <MMC0_CMD &pcfg_pull_none>;
+ };
- sd0_cd: sd0-cd {
- rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd0_cd: sd0-cd {
+ rockchip,pins = <MMC0_DETN &pcfg_pull_none>;
+ };
- sd0_wp: sd0-wp {
- rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd0_wp: sd0-wp {
+ rockchip,pins = <MMC0_WRPRT &pcfg_pull_none>;
+ };
- sd0_pwr: sd0-pwr {
- rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd0_pwr: sd0-pwr {
+ rockchip,pins = <MMC0_PWREN &pcfg_pull_none>;
+ };
- sd0_bus1: sd0-bus-width1 {
- rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd0_bus1: sd0-bus-width1 {
+ rockchip,pins = <MMC0_D0 &pcfg_pull_none>;
+ };
- sd0_bus4: sd0-bus-width4 {
- rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd0_bus4: sd0-bus-width4 {
+ rockchip,pins = <MMC0_D0 &pcfg_pull_none>,
+ <MMC0_D1 &pcfg_pull_none>,
+ <MMC0_D2 &pcfg_pull_none>,
+ <MMC0_D3 &pcfg_pull_none>;
};
+ };
- sd1 {
- sd1_clk: sd1-clk {
- rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
- };
+
+ sd1 {
+ sd1_clk: sd1-clk {
+ rockchip,pins = <MMC1_CLKOUT &pcfg_pull_none>;
+ };
- sd1_cmd: sd1-cmd {
- rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd1_cmd: sd1-cmd {
+ rockchip,pins = <MMC1_CMD &pcfg_pull_none>;
+ };
- sd1_cd: sd1-cd {
- rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd1_cd: sd1-cd {
+ rockchip,pins = <MMC1_DETN &pcfg_pull_none>;
+ };
- sd1_wp: sd1-wp {
- rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd1_wp: sd1-wp {
+ rockchip,pins = <MMC1_WRPRT &pcfg_pull_none>;
+ };
- sd1_bus1: sd1-bus-width1 {
- rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd1_bus1: sd1-bus-width1 {
+ rockchip,pins = <MMC1_D0 &pcfg_pull_none>;
+ };
- sd1_bus4: sd1-bus-width4 {
- rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
- <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
- };
+ sd1_bus4: sd1-bus-width4 {
+ rockchip,pins = <MMC1_D0 &pcfg_pull_none>,
+ <MMC1_D1 &pcfg_pull_none>,
+ <MMC1_D2 &pcfg_pull_none>,
+ <MMC1_D3 &pcfg_pull_none>;
};
};
+ };
uart0: serial@10124000 {
wake-irq = <0>;
status = "disabled";
};
-
- /*sample code for gpio*/
- leds {
- compatible = "gpio-leds";
-
- d2 {
- label = "d2";
- gpios = <&gpio0 2 1>; /* GPIO0-2 level1*/
- };
- };
};
--- /dev/null
+/*
+ * Header providing constants for Rockchip pinctrl bindings.
+ *
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__
+#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__
+
+
+/* GPIO0_A */
+/* GPIO0_B */
+/* GPIO0_C */
+#define GPIO0_C0 0x0c00
+#define NAND_D8 0x0c01
+
+#define GPIO0_C1 0x0c10
+#define NAND_D9 0x0c11
+
+#define GPIO0_C2 0x0c20
+#define NAND_D10 0x0c21
+
+#define GPIO0_C3 0x0c30
+#define NAND_D11 0x0c31
+
+#define GPIO0_C4 0x0c40
+#define NAND_D12 0x0c41
+
+#define GPIO0_C5 0x0c50
+#define NAND_D13 0x0c51
+
+#define GPIO0_C6 0x0c60
+#define NAND_D14 0x0c61
+
+#define GPIO0_C7 0x0c70
+#define NAND_D15 0x0c71
+
+
+/* GPIO0_D */
+#define GPIO0_D0 0x0d00
+#define NAND_DQS 0x0d01
+#define EMMC_CLKOUT 0x0d02
+
+#define GPIO0_D1 0x0d10
+#define NAND_CS1 0x0d11
+
+#define GPIO0_D2 0x0d20
+#define NAND_CS2 0x0d21
+#define EMMC_CMD 0x0d22
+
+#define GPIO0_D3 0x0d30
+#define NAND_CS3 0x0d31
+#define EMMC_RSTNOUT 0x0d32
+
+#define GPIO0_D4 0x0d40
+#define SPI1_RXD 0x0d41
+
+#define GPIO0_D5 0x0d50
+#define SPI1_TXD 0x0d51
+
+#define GPIO0_D6 0x0d60
+#define SPI1_CLK 0x0d61
+
+#define GPIO0_D7 0x0d70
+#define SPI1_CS0 0x0d71
+
+
+/* GPIO1_A */
+#define GPIO1_A0 0x1a00
+#define UART0_SIN 0x1a01
+
+#define GPIO1_A1 0x1a10
+#define UART0_SOUT 0x1a11
+
+#define GPIO1_A2 0x1a20
+#define UART0_CTSN 0x1a21
+
+#define GPIO1_A3 0x1a30
+#define UART0_RTSN 0x1a31
+
+#define GPIO1_A4 0x1a40
+#define UART1_SIN 0x1a41
+#define SPI0_RXD 0x1a42
+
+#define GPIO1_A5 0x1a50
+#define UART1_SOUT 0x1a51
+#define SPI0_TXD 0x1a52
+
+#define GPIO1_A6 0x1a60
+#define UART1_CTSN 0x1a61
+#define SPI0_CLK 0x1a62
+
+#define GPIO1_A7 0x1a70
+#define UART1_RTSN 0x1a71
+#define SPI0_CS0 0x1a72
+
+/* GPIO1_B */
+#define GPIO1_B0 0x1b00
+#define UART2_SIN 0x1b01
+#define JTAG_TDI 0x1b02
+
+#define GPIO1_B1 0x1b10
+#define UART2_SOUT 0x1b11
+#define JTAG_TDO 0x1b12
+
+#define GPIO1_B2 0x1b20
+#define UART3_SIN 0x1b21
+#define GPS_MAG 0x1b22
+
+#define GPIO1_B3 0x1b30
+#define UART3_SOUT 0x1b31
+#define GPS_SIG 0x1b32
+
+#define GPIO1_B4 0x1b40
+#define UART3_CTSN 0x1b41
+#define GPS_RFCLK 0x1b42
+
+#define GPIO1_B5 0x1b50
+#define UART3_RTSN 0x1b51
+
+#define GPIO1_B6 0x1b60
+#define SPDIF_TX 0x1b61
+#define SPI1_CS1 0x1b62
+
+#define GPIO1_B7 0x1b70
+#define SPI0_CS1 0x1b71
+
+
+/* GPIO1_C */
+#define GPIO1_C0 0x1c00
+#define I2S0_MCLK 0x1c01
+
+#define GPIO1_C1 0x1c10
+#define I2S0_SCLK 0x1c11
+
+#define GPIO1_C2 0x1c20
+#define I2S0_LRCKRX 0x1c21
+
+#define GPIO1_C3 0x1c30
+#define I2S0_LRCKTX 0x1c31
+
+#define GPIO1_C4 0x1c40
+#define I2S0_SDI 0x1c41
+
+#define GPIO1_C5 0x1c50
+#define I2S0_SDO 0x1c51
+
+
+/* GPIO1_D */
+#define GPIO1_D0 0x1d00
+#define I2C0_SDA 0x1d01
+
+#define GPIO1_D1 0x1d10
+#define I2C0_SCL 0x1d11
+
+#define GPIO1_D2 0x1d20
+#define I2C1_SDA 0x1d21
+
+#define GPIO1_D3 0x1d30
+#define I2C1_SCL 0x1d31
+
+#define GPIO1_D4 0x1d40
+#define I2C2_SDA 0x1d41
+
+#define GPIO1_D5 0x1d50
+#define I2C2_SCL 0x1d51
+
+#define GPIO1_D6 0x1d60
+#define I2C4_SDA 0x1d61
+
+#define GPIO1_D7 0x1d70
+#define I2C4_SCL 0x1d71
+
+
+/* GPIO2_A */
+#define GPIO2_A0 0x2a00
+#define LCDC1_D0 0x2a01
+#define SMC_D0 0x2a02
+#define TRACE_D0 0x2a03
+
+#define GPIO2_A1 0x2a10
+#define LCDC1_D1 0x2a11
+#define SMC_D1 0x2a12
+#define TRACE_D1 0x2a13
+
+#define GPIO2_A2 0x2a20
+#define LCDC1_D2 0x2a21
+#define SMC_D2 0x2a22
+#define TRACE_D2 0x2a23
+
+#define GPIO2_A3 0x2a30
+#define LCDC1_D3 0x2a31
+#define SMC_D3 0x2a32
+#define TRACE_D3 0x2a33
+
+#define GPIO2_A4 0x2a40
+#define LCDC1_D4 0x2a41
+#define SMC_D4 0x2a42
+#define TRACE_D4 0x2a43
+
+#define GPIO2_A5 0x2a50
+#define LCDC1_D5 0x2a51
+#define SMC_D5 0x2a52
+#define TRACE_D5 0x2a53
+
+#define GPIO2_A6 0x2a60
+#define LCDC1_D6 0x2a61
+#define SMC_D6 0x2a62
+#define TRACE_D6 0x2a63
+
+#define GPIO2_A7 0x2a70
+#define LCDC1_D7 0x2a71
+#define SMC_D7 0x2a72
+#define TRACE_D7 0x2a73
+
+
+/* GPIO2_B */
+#define GPIO2_B0 0x2b00
+#define LCDC1_D8 0x2b01
+#define SMC_D8 0x2b02
+#define TRACE_D8 0x2b03
+
+#define GPIO2_B1 0x2b10
+#define LCDC1_D9 0x2b11
+#define SMC_D9 0x2b11
+#define TRACE_D9 0x2b12
+
+#define GPIO2_B2 0x2b20
+#define LCDC1_D10 0x2b21
+#define SMC_D10 0x2b22
+#define TRACE_D10 0x2b23
+
+#define GPIO2_B3 0x2b30
+#define LCDC1_D11 0x2b31
+#define SMC_D11 0x2b32
+#define TRACE_D11 0x2b33
+
+#define GPIO2_B4 0x2b40
+#define LCDC1_D12 0x2b41
+#define SMC_D12 0x2b42
+#define TRACE_D12 0x2b43
+
+#define GPIO2_B5 0x2b50
+#define LCDC1_D13 0x2b51
+#define SMC_D13 0x2b52
+#define TRACE_D13 0x2b53
+
+#define GPIO2_B6 0x2b60
+#define LCDC1_D14 0x2b61
+#define SMC_D14 0x2b62
+#define TRACE_D14 0x2b63
+
+
+#define GPIO2_B7 0x2b70
+#define LCDC1_D15 0x2b71
+#define SMC_D15 0x2b72
+#define TRACE_D15 0x2b73
+
+
+/* GPIO2_C */
+#define GPIO2_C0 0x2c00
+#define LCDC1_D16 0x2c01
+#define SMC_R0 0x2c02
+#define TRACE_CLK 0x2c03
+
+#define GPIO2_C1 0x2c10
+#define LCDC1_D17 0x2c11
+#define SMC_R1 0x2c12
+#define TRACE_CTL 0x2c13
+
+#define GPIO2_C2 0x2c20
+#define LCDC1_D18 0x2c21
+#define SMC_R2 0x2c22
+
+#define GPIO2_C3 0x2c30
+#define LCDC1_D19 0x2c31
+#define SMC_R3 0x2c32
+
+#define GPIO2_C4 0x2c40
+#define LCDC1_D20 0x2c41
+#define SMC_R4 0x2c42
+
+#define GPIO2_C5 0x2c50
+#define LCDC1_D21 0x2c51
+#define SMC_R5 0x2c52
+
+#define GPIO2_C6 0x2c60
+#define LCDC1_D22 0x2c61
+#define SMC_R6 0x2c62
+
+#define GPIO2_C7 0x2c70
+#define LCDC1_D23 0x2c71
+#define SMC_R7 0x2c72
+
+
+/* GPIO2_D */
+#define GPIO2_D0 0x2d00
+#define LCDC1_DCLK 0x2d01
+#define SMC_CS0 0x2d02
+
+#define GPIO2_D1 0x2d10
+#define LCDC1_DEN 0x2d11
+#define SMC_WEN 0x2d12
+
+#define GPIO2_D2 0x2d20
+#define LCDC1_HSYNC 0x2d21
+#define SMC_OEN 0x2d22
+
+#define GPIO2_D3 0x2d30
+#define LCDC1_VSYNC 0x2d31
+#define SMC_ADVN 0x2d32
+
+#define GPIO2_D4 0x2d40
+#define SMC_BLSN0 0x2d41
+
+#define GPIO2_D5 0x2d50
+#define SMC_BLSN1 0x2d51
+
+#define GPIO2_D6 0x2d60
+#define SMC_CS1 0x2d61
+
+#define GPIO2_D7 0x2d70
+#define TEST_CLK_OUT 0x2d71
+
+
+/* GPIO3_A */
+#define GPIO3_A0 0x3a00
+#define MMC0_RSTNOUT 0x3a01
+
+#define GPIO3_A1 0x3a10
+#define MMC0_PWREN 0x3a11
+
+#define GPIO3_A2 0x3a20
+#define MMC0_CLKOUT 0x3a21
+
+#define GPIO3_A3 0x3a30
+#define MMC0_CMD 0x3a31
+
+#define GPIO3_A4 0x3a40
+#define MMC0_D0 0x3a41
+
+#define GPIO3_A5 0x3a50
+#define MMC0_D1 0x3a51
+
+#define GPIO3_A6 0x3a60
+#define MMC0_D2 0x3a61
+
+#define GPIO3_A7 0x3a70
+#define MMC0_D3 0x3a71
+
+
+/* GPIO3_B */
+#define GPIO3_B0 0x3b00
+#define MMC0_DETN 0x3b01
+
+#define GPIO3_B1 0x3b10
+#define MMC0_WRPRT 0x3b11
+
+#define GPIO3_B3 0x3b30
+#define CIF0_CLKOUT 0x3b31
+
+#define GPIO3_B4 0x3b40
+#define CIF0_D0 0x3b41
+#define HSADC_D8 0x3b42
+
+#define GPIO3_B5 0x3b50
+#define CIF0_D1 0x3b51
+#define HSADC_D9 0x3b52
+
+#define GPIO3_B6 0x3b60
+#define CIF0_D10 0x3b61
+#define I2C3_SDA 0x3b62
+
+#define GPIO3_B7 0x3b70
+#define CIF0_D11 0x3b71
+#define I2C3_SCL 0x3b72
+
+
+/* GPIO3_C */
+#define GPIO3_C0 0x3c00
+#define MMC1_CMD 0x3c01
+#define RMII_TXEN 0x3c02
+
+#define GPIO3_C1 0x3c10
+#define MMC1_D0 0x3c11
+#define RMII_TXD1 0x3c12
+
+#define GPIO3_C2 0x3c20
+#define MMC1_D1 0x3c21
+#define RMII_TXD0 0x3c22
+
+#define GPIO3_C3 0x3c30
+#define MMC1_D2 0x3c31
+#define RMII_RXD0 0x3c32
+
+#define GPIO3_C4 0x3c40
+#define MMC1_D3 0x3c41
+#define RMII_RXD1 0x3c42
+
+#define GPIO3_C5 0x3c50
+#define MMC1_CLKOUT 0x3c51
+#define RMII_CLKOUT 0x3c52
+#define RMII_CLKIN 0x3c52
+
+#define GPIO3_C6 0x3c60
+#define MMC1_DETN 0x3c61
+#define RMII_RXERR 0x3c62
+
+#define GPIO3_C7 0x3c70
+#define MMC1_WRPRT 0x3c71
+#define RMII_CRS 0x3c72
+
+
+/* GPIO3_D */
+#define GPIO3_D0 0x3d00
+#define MMC1_PWREN 0x3d01
+#define RMII_MD 0x3d02
+
+#define GPIO3_D1 0x3d10
+#define MMC1_BKEPWR 0x3d11
+#define RMII_MDCLK 0x3d12
+
+#define GPIO3_D2 0x3d20
+#define MMC1_INTN 0x3d21
+
+#define GPIO3_D3 0x3d30
+#define PWM0 0x3d31
+
+#define GPIO3_D4 0x3d40
+#define PWM1 0x3d41
+#define JTAG_TRSTN 0x3d42
+
+#define GPIO3_D5 0x3d50
+#define PWM2 0x3d51
+#define JTAG_TCK 0x3d52
+#define OTG_DRV_VBUS 0x3d53
+
+#define GPIO3_D6 0x3d60
+#define PWM3 0x3d61
+#define JTAG_TMS 0x3d62
+#define HOST_DRV_VBUS 0x3d63
+
+
+#define VOL_DOMAIN_DEFAULT 0
+#define VOL_DOMAIN_10V 1
+#define VOL_DOMAIN_12V 2
+#define VOL_DOMAIN_18V 3
+#define VOL_DOMAIN_30V 4
+#define VOL_DOMAIN_33V 5
+#define VOL_DOMAIN_50V 6
+
+
+//#define rk29_mux_api_set(name, mode) iomux_set(mode)
+//#define rk30_mux_api_set(name, mode) iomux_set(mode)
+//#define rk30_iomux_init() iomux_init()
+
+#define NUM_GROUP 32
+#define PIN_BASE 0
+
+#define RK30_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
+#define RK30_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
+#define RK30_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
+#define RK30_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
+#define RK30_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
+#define RK30_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
+#define RK30_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
+#define RK30_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
+#define RK30_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
+#define RK30_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
+#define RK30_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
+#define RK30_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
+#define RK30_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
+#define RK30_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
+#define RK30_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
+#define RK30_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
+#define RK30_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
+#define RK30_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
+#define RK30_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
+#define RK30_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
+#define RK30_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
+#define RK30_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
+#define RK30_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
+#define RK30_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
+#define RK30_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
+#define RK30_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
+#define RK30_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
+#define RK30_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
+#define RK30_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
+#define RK30_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
+#define RK30_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
+#define RK30_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
+
+#define RK30_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
+#define RK30_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
+#define RK30_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
+#define RK30_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
+#define RK30_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
+#define RK30_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
+#define RK30_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
+#define RK30_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
+#define RK30_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
+#define RK30_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
+#define RK30_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
+#define RK30_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
+#define RK30_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
+#define RK30_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
+#define RK30_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
+#define RK30_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
+#define RK30_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
+#define RK30_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
+#define RK30_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
+#define RK30_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
+#define RK30_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
+#define RK30_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
+#define RK30_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
+#define RK30_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
+#define RK30_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
+#define RK30_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
+#define RK30_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
+#define RK30_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
+#define RK30_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
+#define RK30_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
+#define RK30_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
+#define RK30_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
+
+#define RK30_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
+#define RK30_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
+#define RK30_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
+#define RK30_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
+#define RK30_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
+#define RK30_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
+#define RK30_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
+#define RK30_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
+#define RK30_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
+#define RK30_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
+#define RK30_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
+#define RK30_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
+#define RK30_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
+#define RK30_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
+#define RK30_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
+#define RK30_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
+#define RK30_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
+#define RK30_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
+#define RK30_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
+#define RK30_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
+#define RK30_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
+#define RK30_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
+#define RK30_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
+#define RK30_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
+#define RK30_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
+#define RK30_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
+#define RK30_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
+#define RK30_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
+#define RK30_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
+#define RK30_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
+#define RK30_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
+#define RK30_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
+
+#define RK30_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
+#define RK30_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
+#define RK30_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
+#define RK30_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
+#define RK30_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
+#define RK30_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
+#define RK30_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
+#define RK30_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
+#define RK30_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
+#define RK30_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
+#define RK30_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
+#define RK30_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
+#define RK30_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
+#define RK30_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
+#define RK30_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
+#define RK30_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
+#define RK30_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
+#define RK30_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
+#define RK30_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
+#define RK30_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
+#define RK30_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
+#define RK30_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
+#define RK30_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
+#define RK30_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
+#define RK30_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
+#define RK30_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
+#define RK30_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
+#define RK30_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
+#define RK30_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
+#define RK30_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
+#define RK30_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
+#define RK30_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
+
+#define RK30_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0)
+#define RK30_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1)
+#define RK30_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2)
+#define RK30_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3)
+#define RK30_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4)
+#define RK30_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5)
+#define RK30_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6)
+#define RK30_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7)
+#define RK30_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8)
+#define RK30_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9)
+#define RK30_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10)
+#define RK30_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11)
+#define RK30_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12)
+#define RK30_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13)
+#define RK30_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14)
+#define RK30_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15)
+#define RK30_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16)
+#define RK30_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17)
+#define RK30_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18)
+#define RK30_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19)
+#define RK30_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20)
+#define RK30_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21)
+#define RK30_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22)
+#define RK30_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23)
+#define RK30_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24)
+#define RK30_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25)
+#define RK30_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26)
+#define RK30_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27)
+#define RK30_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28)
+#define RK30_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29)
+#define RK30_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30)
+#define RK30_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31)
+
+#define RK30_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0)
+#define RK30_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1)
+#define RK30_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2)
+#define RK30_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3)
+#define RK30_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4)
+#define RK30_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
+#define RK30_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
+#define RK30_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
+#define RK30_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
+#define RK30_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
+#define RK30_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
+#define RK30_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11)
+#define RK30_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12)
+#define RK30_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13)
+#define RK30_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
+#define RK30_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)
+
+
+#endif
projects / firefly-linux-kernel-4.4.55.git / commitdiff