clk: rockchip: rk3288: add ddrc clock support

Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3288 platform in future.

Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index c9c32f0acb074c861087a5f41ab2774af39e7246..6c2e24b0e7b7c768fa47b612a87b89dde3eb5ffa 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -308,6 +308,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKGATE_CON(0), 8, GFLAGS),
        GATE(0, "gpll_ddr", "gpll", 0,
                        RK3288_CLKGATE_CON(0), 9, GFLAGS),
+       COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
+                        RK3288_CLKSEL_CON(26), 2, 1, 0, 0,
+                        ROCKCHIP_DDRCLK_SIP),
        COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
                                        DFLAGS | CLK_DIVIDER_POWER_OF_TWO),