visible impact on the overall performance or power consumption of the
processor.
-config ARM_ERRATA_720791
- bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream"
- depends on CPU_V7
- help
- This option enables the workaround for the 720791 Cortex-A9
- (r1p0..r1p2) erratum. The Jazelle instruction stream may be
- corrupted when dynamic high-level clock gating is enabled.
- This workaround disables gating the Core clock when the Instruction
- side is waiting for a Page Table Walk answer or linefill completion.
-
endmenu
source "arch/arm/common/Kconfig"
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
- cmp r6, #0x10 @ power ctrl reg added r1p0
- mrcge p15, 0, r10, c15, c0, 0 @ read power control register
- orrge r10, r10, #1 @ enable dynamic clock gating
- mcrge p15, 0, r10, c15, c0, 0 @ write power control register
-#ifdef CONFIG_ARM_ERRATA_720791
- teq r5, #0x00100000 @ only present in r1p*
- mrceq p15, 0, r10, c15, c0, 2 @ read "chicken power ctrl" reg
- orreq r10, r10, #0x30 @ disable core clk gate on
- mcreq p15, 0, r10, c15, c0, 2 @ instr-side waits
-#endif
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 @ only present up to r2p2
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register