drm/i915: correct FBC update when pipe base update occurs

We usually don't have an SAREA, and we always want to update the FBC
status anyway, so move the update up above the various master/sarea
checks.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 44234150e8421496bd3f05479b60fa5221f8ac66..cb0f4f96439ed659cb05b540d58defbf1ccf4d7a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1260,6 +1260,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                I915_READ(dspbase);
        }
 
+       if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
+               intel_update_fbc(crtc, &crtc->mode);
+
        intel_wait_for_vblank(dev);
 
        if (old_fb) {
@@ -1286,9 +1289,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                master_priv->sarea_priv->pipeA_y = y;
        }
 
-       if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
-               intel_update_fbc(crtc, &crtc->mode);
-
        return 0;
 }