O << "\"";
for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
- unsigned char C =
+ unsigned char C =
(unsigned char)cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
if (C == '"') {
/// emitGlobalConstant - Print a general LLVM constant to the .s file.
///
-void AsmPrinter::emitGlobalConstant(const Constant *CV) {
+void AsmPrinter::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData();
if (CV->isNullValue() || isa<UndefValue>(CV)) {
int32_t UVal;
} U;
U.FVal = (float)Val;
-
+
O << Data32bitsDirective << U.UVal << "\t" << CommentString
<< " float " << Val << "\n";
return;
} else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) {
if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
uint64_t Val = CI->getRawValue();
-
+
if (Data64bitsDirective)
O << Data64bitsDirective << Val << "\n";
else if (TD.isBigEndian()) {
const Type *type = CV->getType();
switch (type->getTypeID()) {
- case Type::BoolTyID:
+ case Type::BoolTyID:
case Type::UByteTyID: case Type::SByteTyID:
O << Data8bitsDirective;
break;
case Type::UIntTyID: case Type::IntTyID:
O << Data32bitsDirective;
break;
- case Type::ULongTyID: case Type::LongTyID:
+ case Type::ULongTyID: case Type::LongTyID:
assert (0 && "Should have already output double-word constant.");
case Type::FloatTyID: case Type::DoubleTyID:
assert (0 && "Should have already output floating point constant.");
//===-- BranchFolding.cpp - Fold machine code branch instructions ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass forwards branches to unconditional branches to make them branch
assert(Br->getNumOperands() == 1 && Br->getOperand(0).isMachineBasicBlock()
&& "Uncond branch should take one MBB argument!");
MachineBasicBlock *Dest = Br->getOperand(0).getMachineBasicBlock();
-
+
while (!MBB->pred_empty()) {
MachineBasicBlock *Pred = *(MBB->pred_end()-1);
ReplaceUsesOfBlockWith(Pred, MBB, Dest, TII);
//===-- IntrinsicLowering.cpp - Intrinsic Lowering default implementation -===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the default intrinsic lowering implementation.
void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
Function *Callee = CI->getCalledFunction();
assert(Callee && "Cannot lower an indirect call!");
-
+
switch (Callee->getIntrinsicID()) {
case Intrinsic::not_intrinsic:
std::cerr << "Cannot lower a call to a non-intrinsic function '"
CI->replaceAllUsesWith(V);
break;
}
- case Intrinsic::sigsetjmp:
+ case Intrinsic::sigsetjmp:
if (CI->getType() != Type::VoidTy)
CI->replaceAllUsesWith(Constant::getNullValue(CI->getType()));
break;
case Intrinsic::returnaddress:
case Intrinsic::frameaddress:
std::cerr << "WARNING: this target does not support the llvm."
- << (Callee->getIntrinsicID() == Intrinsic::returnaddress ?
+ << (Callee->getIntrinsicID() == Intrinsic::returnaddress ?
"return" : "frame") << "address intrinsic.\n";
CI->replaceAllUsesWith(ConstantPointerNull::get(
cast<PointerType>(CI->getType())));
break;
}
}
-
+
assert(CI->use_empty() &&
"Lowering should have eliminated any uses of the intrinsic call!");
CI->getParent()->getInstList().erase(CI);
//
bool LiveInterval::liveAt(unsigned I) const {
Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
-
+
if (r == ranges.begin())
return false;
/// extendIntervalStartTo - This method is used when we want to extend the range
/// specified by I to start at the specified endpoint. To do this, we should
/// merge and eliminate all ranges that this will overlap with.
-LiveInterval::Ranges::iterator
+LiveInterval::Ranges::iterator
LiveInterval::extendIntervalStartTo(Ranges::iterator I, unsigned NewStart) {
assert(I != ranges.end() && "Not a valid interval!");
unsigned ValId = I->ValId;
// Get the register classes for the first reg.
if (MRegisterInfo::isPhysicalRegister(RegA)) {
- assert(MRegisterInfo::isVirtualRegister(RegB) &&
+ assert(MRegisterInfo::isVirtualRegister(RegB) &&
"Shouldn't consider two physregs!");
return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
}
}
LiveInterval LiveIntervals::createInterval(unsigned reg) {
- float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
+ float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
(float)HUGE_VAL :0.0F;
return LiveInterval(reg, Weight);
}
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the LiveVariable analysis pass. For each machine
// instruction in the function, this pass calculates the set of registers that
// are immediately dead after the instruction (i.e., the instruction calculates
assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif
- assert(MBB != VRInfo.DefInst->getParent() &&
+ assert(MBB != VRInfo.DefInst->getParent() &&
"Should have kill for defblock!");
// Add a new kill entry for this basic block.
// physical register. This is a purely local property, because all physical
// register references as presumed dead across basic blocks.
//
- PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
+ PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
RegInfo->getNumRegs());
PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
"Cannot have a live-in virtual register!");
HandlePhysRegDef(*I, 0);
}
-
+
// Calculate live variable information in depth first order on the CFG of the
// function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for PHI
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
// of the uses. They will be handled in other basic blocks.
- if (MI->getOpcode() == TargetInstrInfo::PHI)
+ if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1;
// Loop over implicit uses, using them.
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
E = MBB->succ_end(); SI != E; ++SI) {
MachineBasicBlock *Succ = *SI;
-
+
// PHI nodes are guaranteed to be at the top of the block...
for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
}
}
}
-
+
// Finally, if the last block in the function is a return, make sure to mark
// it as using all of the live-out values in the function.
if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
// function. If so, it is due to a bug in the instruction selector or some
// other part of the code generator if this happens.
#ifndef NDEBUG
- for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
+ for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
#endif
}
void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
- std::vector<MachineBasicBlock *>::iterator I =
+ std::vector<MachineBasicBlock *>::iterator I =
std::find(Predecessors.begin(), Predecessors.end(), pred);
assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
Predecessors.erase(I);
//===-- MachineCodeEmitter.cpp - Implement the MachineCodeEmitter itf -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the MachineCodeEmitter interface.
std::cout << "\n--- End of stub for Function\n";
return 0;
}
-
+
void emitByte(unsigned char B) {
std::cout << "0x" << std::hex << (unsigned int)B << std::dec << " ";
}
MachineCodeEmitter &MCE;
unsigned counter;
unsigned values[4];
-
+
public:
FilePrinterEmitter(MachineCodeEmitter &M, std::ostream &os)
: o(os), MCE(M), counter(0) {
openActual();
}
-
- ~FilePrinterEmitter() {
+
+ ~FilePrinterEmitter() {
o << "\n";
actual.close();
}
void *finishFunctionStub(const Function *F) {
return MCE.finishFunctionStub(F);
}
-
+
void emitByte(unsigned char B) {
MCE.emitByte(B);
actual << B; actual.flush();
/// CreateStackObject - Create a stack object for a value of the specified type.
///
int MachineFrameInfo::CreateStackObject(const Type *Ty, const TargetData &TD) {
- return CreateStackObject((unsigned)TD.getTypeSize(Ty),
+ return CreateStackObject((unsigned)TD.getTypeSize(Ty),
TD.getTypeAlignment(Ty));
}
//===-- MachineInstr.cpp --------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Methods common to all machine instructions.
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
// This variable is initialized and reset by class TargetInstrInfo.
-//
+//
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
/// replace - Support for replacing opcode and operands of a MachineInstr in
/// place. This only resets the size of the operand vector and initializes it.
/// The new operands must be set explicitly later.
-///
+///
void MachineInstr::replace(short opcode, unsigned numOperands) {
assert(getNumImplicitRefs() == 0 &&
"This is probably broken because implicit refs are going to be lost.");
{
assert((!defsOnly || !notDefsAndUses) &&
"notDefsAndUses is irrelevant if defsOnly == true.");
-
+
unsigned numSubst = 0;
// Substitute operands
static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine *TM) {
const MRegisterInfo *MRI = 0;
-
+
if (TM) MRI = TM->getRegisterInfo();
bool CloseParen = true;
OS << "%hm(";
else
CloseParen = false;
-
+
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (MO.getVRegValue()) {
// be attached to a Machine function yet
if (TM)
OS << TM->getInstrInfo()->getName(getOpcode());
-
+
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i);
if (i != StartOp)
OS << ",";
OS << " ";
::print(mop, OS, TM);
-
+
if (mop.isDef())
if (mop.isUse())
OS << "<def&use>";
else
OS << "<def>";
}
-
+
// code for printing implicit references
if (getNumImplicitRefs()) {
OS << "\tImplicitRefs: ";
OS << "<def>";
}
}
-
+
OS << "\n";
}
// Otherwise, print it out in the "raw" format without symbolic register names
// and such.
os << TargetInstrDescriptors[MI.getOpcode()].Name;
-
+
for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
if (MI.getOperand(i).isDef())
else
os << "<d>";
}
-
+
// code for printing implicit references
unsigned NumOfImpRefs = MI.getNumImplicitRefs();
if (NumOfImpRefs > 0) {
os << "\tImplicit: ";
for (unsigned z = 0; z < NumOfImpRefs; z++) {
- OutputValue(os, MI.getImplicitRef(z));
+ OutputValue(os, MI.getImplicitRef(z));
if (MI.getImplicitOp(z).isDef())
if (MI.getImplicitOp(z).isUse())
os << "<d&u>";
os << "\t";
}
}
-
+
return os << "\n";
}
OS << "%hh(";
else if (MO.isLoBits64())
OS << "%hm(";
-
+
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
assert(0 && "Unrecognized operand type");
break;
}
-
+
if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
OS << ")";
-
+
return OS;
}
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass eliminates machine instruction PHI nodes by inserting copy
while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
// Unlink the PHI node from the basic block, but don't delete the PHI yet.
MachineInstr *MPhi = MBB.remove(MBB.begin());
-
+
assert(MRegisterInfo::isVirtualRegister(MPhi->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
unsigned DestReg = MPhi->getOperand(0).getReg();
-
+
// Create a new register for the incoming PHI arguments
const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
// into the phi node destination.
//
RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
-
+
// Update live variable information if there is any...
if (LV) {
MachineInstr *PHICopy = prior(AfterPHIsIt);
// of any registers, or if the value itself is dead, we need to move this
// information over to the new copy we just inserted.
//
- std::pair<LiveVariables::killed_iterator, LiveVariables::killed_iterator>
+ std::pair<LiveVariables::killed_iterator, LiveVariables::killed_iterator>
RKs = LV->killed_range(MPhi);
std::vector<std::pair<MachineInstr*, unsigned> > Range;
if (RKs.first != RKs.second) // Delete the range.
//
for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
MachineOperand &opVal = MPhi->getOperand(i-1);
-
+
// Get the MachineBasicBlock equivalent of the BasicBlock that is the
// source path the PHI.
MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock();
MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
-
+
// Check to make sure we haven't already emitted the copy for this block.
// This can happen because PHI nodes may have multiple entries for the
// same basic block. It doesn't matter which entry we use though, because
// register we are interested in!
//
bool HaveNotEmitted = true;
-
+
if (I != opBlock.begin()) {
MachineBasicBlock::iterator PrevInst = prior(I);
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
if (MO.isDef()) {
HaveNotEmitted = false;
break;
- }
+ }
}
}
for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) {
MachineBasicBlock *SuccMBB = *SI;
-
+
// Is it alive in this successor?
unsigned SuccIdx = SuccMBB->getNumber();
if (SuccIdx < InRegVI.AliveBlocks.size() &&
ValueIsLive = true;
break;
}
-
+
// Is it killed in this successor?
for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
if (InRegVI.Kills[i]->getParent() == SuccMBB) {
if (!ValueIsLive)
ValueIsLive = VRegPHIUseCount[SrcReg] != 0;
}
-
+
// Okay, if we now know that the value is not live out of the block,
// we can add a kill marker to the copy we inserted saying that it
// kills the incoming value!
}
}
}
-
+
// Really delete the PHI instruction now!
delete MPhi;
}
//===-- Passes.cpp - Target independent code generation passes ------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines interfaces to access the target independent code
//===-- PrologEpilogInserter.cpp - Insert Prolog/Epilog code in function --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass is responsible for finalizing the functions frame layout, saving
void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
// Early exit if no caller saved registers are modified!
if (RegsToSave.empty())
- return;
+ return;
const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
///
void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
-
+
bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
-
+
// Loop over all of the stack objects, assigning sequential addresses...
MachineFrameInfo *FFI = Fn.getFrameInfo();
int Offset = TFI.getOffsetOfLocalArea();
if (StackGrowsDown)
Offset = -Offset;
- assert(Offset >= 0
+ assert(Offset >= 0
&& "Local area offset should be in direction of stack growth");
// If there are fixed sized objects that are preallocated in the local area,
// non-fixed objects can't be allocated right at the start of local area.
- // We currently don't support filling in holes in between fixed sized objects,
+ // We currently don't support filling in holes in between fixed sized objects,
// so we adjust 'Offset' to point to the end of last fixed sized
// preallocated object.
for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
// the offset is negative, so we negate the offset to get the distance.
FixedOff = -FFI->getObjectOffset(i);
} else {
- // The maximum distance from the start pointer is at the upper
+ // The maximum distance from the start pointer is at the upper
// address of the object.
FixedOff = FFI->getObjectOffset(i) + FFI->getObjectSize(i);
- }
- if (FixedOff > Offset) Offset = FixedOff;
+ }
+ if (FixedOff > Offset) Offset = FixedOff;
}
for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
assert(Align <= StackAlignment && "Cannot align stack object to higher "
"alignment boundary than the stack itself!");
Offset = (Offset+Align-1)/Align*Align; // Adjust to Alignment boundary...
-
+
if (StackGrowsDown) {
FFI->setObjectOffset(i, -Offset); // Set the computed offset
} else {
- FFI->setObjectOffset(i, Offset);
+ FFI->setObjectOffset(i, Offset);
Offset += FFI->getObjectSize(i);
}
}
assert(MRegisterInfo::isVirtualRegister(cur->reg) &&
"Can only allocate virtual registers!");
-
+
// Allocating a virtual register. try to find a free
// physical register or spill an interval (possibly this one) in order to
// assign it one.
active_[i] = active_.back();
active_.pop_back();
--i; --e;
-
+
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
DEBUG(std::cerr << "\t\tinterval " << *Interval << " inactive\n");
unsigned reg = Interval->reg;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
-
+
if (IntervalPos == Interval->end()) { // remove expired intervals.
DEBUG(std::cerr << "\t\tinterval " << *Interval << " expired\n");
/// updateSpillWeights - updates the spill weights of the specifed physical
/// register and its weight.
-static void updateSpillWeights(std::vector<float> &Weights,
+static void updateSpillWeights(std::vector<float> &Weights,
unsigned reg, float weight,
const MRegisterInfo *MRI) {
Weights[reg] += weight;
///
MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum);
-
+
void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg);
//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements a simple register allocator. *Very* simple: It immediate
const TargetMachine *TM;
const MRegisterInfo *RegInfo;
bool *PhysRegsEverUsed;
-
+
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
std::map<unsigned, int> StackSlotForVirtReg;
// Allocate a new stack object for this spill location...
int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
RC->getAlignment());
-
+
// Assign the slot...
StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
while (1) {
- unsigned regIdx = RegClassIdx[RC]++;
+ unsigned regIdx = RegClassIdx[RC]++;
assert(RI+regIdx != RE && "Not enough registers!");
unsigned PhysReg = *(RI+regIdx);
-
+
if (!RegsUsed[PhysReg]) {
PhysRegsEverUsed[PhysReg] = true;
return PhysReg;
std::map<unsigned, unsigned> Virt2PhysRegMap;
RegsUsed.resize(RegInfo->getNumRegs());
-
+
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
unsigned Opcode = MI->getOpcode();
const unsigned *Regs;
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
RegsUsed[*Regs] = true;
-
+
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
RegsUsed[*Regs] = true;
PhysRegsEverUsed[*Regs] = true;
}
-
+
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
-
+
if (op.isRegister() && op.getReg() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, TM));
-
+
// make sure the same virtual register maps to the same physical
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
}
}
MI->SetMachineOperandReg(i, physReg);
- DEBUG(std::cerr << "virt: " << virtualReg <<
+ DEBUG(std::cerr << "virt: " << virtualReg <<
", phys: " << op.getReg() << "\n");
}
}
//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the SelectionDAG::Legalize method.
VT = MVT::f32;
Extend = true;
}
-
+
SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC),
TLI.getPointerTy());
if (Extend) {
Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2);
else
Result = SDOperand(Node, 0);
-
+
// Since loads produce two values, make sure to remember that we legalized
// both of them.
AddLegalizedOperand(SDOperand(Node, 0), Result);
AddLegalizedOperand(SDOperand(Node, 0), Result);
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
-
+
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1))
case ISD::CopyToReg:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
-
+
switch (getTypeAction(Node->getOperand(1).getValueType())) {
case Legal:
// Legalize the incoming value (must be legal).
break;
case Expand:
SDOperand Lo, Hi;
- ExpandOp(Node->getOperand(1), Lo, Hi);
+ ExpandOp(Node->getOperand(1), Lo, Hi);
unsigned Reg = cast<RegSDNode>(Node)->getReg();
Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
SDOperand Lo, Hi;
ExpandOp(Node->getOperand(1), Lo, Hi);
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
- break;
+ break;
}
case Promote:
Tmp2 = PromoteOp(Node->getOperand(1));
ExpandOp(Node->getOperand(i), Lo, Hi);
NewValues.push_back(Lo);
NewValues.push_back(Hi);
- break;
+ break;
}
case Promote:
assert(0 && "Can't promote multiple return value yet!");
Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
Node->getValueType(0), Tmp1, Tmp2);
break;
- case Expand:
+ case Expand:
SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
if (RHSCST->isAllOnesValue()) {
// Comparison to -1.
Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
- Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
+ Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
Node->getValueType(0), Tmp1, RHSLo);
- break;
+ break;
}
Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
- Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
+ Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
Node->getValueType(0), Tmp1,
DAG.getConstant(0, Tmp1.getValueType()));
break;
// If this is a comparison of the sign bit, just look at the top part.
// X > -1, x < 0
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
- if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
+ if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
CST->getValue() == 0) || // X < 0
(cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
(CST->isAllOnesValue()))) // X > -1
case ISD::SETGE:
case ISD::SETUGE: LowCC = ISD::SETUGE; break;
}
-
+
// Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
// Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
// dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
break;
}
} else {
- Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
+ Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
}
SDOperand Tmp4;
Tmp2 != Node->getOperand(1))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
break;
-
+
case ISD::UREM:
case ISD::SREM:
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1))
- Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
+ Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
Tmp2);
break;
case TargetLowering::Promote:
// In the expand case, we must be dealing with a truncate, because
// otherwise the result would be larger than the source.
ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
-
+
// Since the result is legal, we should just be able to truncate the low
// part of the source.
Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
MachineFunction &MF = DAG.getMachineFunction();
- int SSFI =
+ int SSFI =
MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
case Expand:
ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
// Truncate the low part of the expanded value to the result type
- Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1);
+ Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1);
}
break;
case ISD::SIGN_EXTEND:
// Insert the new chain mapping.
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
break;
- }
+ }
}
assert(Result.Val && "Didn't set a result!");
return true;
case ISD::SRA:
if (Cst > VTBits) {
- Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
+ Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else if (Cst > NVTBits) {
- Lo = DAG.getNode(ISD::SRA, NVT, InH,
+ Lo = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(Cst-NVTBits, ShTy));
- Hi = DAG.getNode(ISD::SRA, NVT, InH,
+ Hi = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else if (Cst == NVTBits) {
Lo = InH;
- Hi = DAG.getNode(ISD::SRA, NVT, InH,
+ Hi = DAG.getNode(ISD::SRA, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else {
Lo = DAG.getNode(ISD::OR, NVT,
DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
DAG.getNode(ISD::SRL, NVT, InL, NAmt));
SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
-
+
Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
} else {
if (Node->hasOneUse()) // Simple case, only has one user to check.
return FindAdjCallStackUp(*Node->use_begin());
-
+
SDOperand TheChain(Node, Node->getNumValues()-1);
assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!");
-
- for (SDNode::use_iterator UI = Node->use_begin(),
+
+ for (SDNode::use_iterator UI = Node->use_begin(),
E = Node->use_end(); ; ++UI) {
assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!");
-
+
// Make sure to only follow users of our token chain.
SDNode *User = *UI;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
SDNode *LatestAdjCallStackUp = 0;
FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown);
//std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n";
-
+
// It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no
// previous call in the function. LatestCallStackDown may in that case be
// the entry node itself. Do not attempt to find a matching ADJCALLSTACKUP
else
LatestAdjCallStackUp = Entry.Val;
assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp");
-
+
SDNode *EarliestAdjCallStackUp = 0;
FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp);
if (EarliestAdjCallStackUp) {
- //std::cerr << "Found node: ";
+ //std::cerr << "Found node: ";
//EarliestAdjCallStackUp->dump(); std::cerr <<"\n";
}
Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
}
SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
-
+
// We don't care about token chains for libcalls. We just use the entry
// node as our input and ignore the output chain. This allows us to place
// calls wherever we need them to satisfy data dependences.
const Type *RetTy = MVT::getTypeForValueType(DestTy);
return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first;
}
-
+
/// ExpandOp - Expand the specified SDOperand into its two component pieces
// Aggregate register values are always in consequtive pairs.
Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
-
+
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
// other one.
SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
-
+
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), TF);
if (!TLI.isLittleEndian())
// The low part is just a sign extension of the input (which degenerates to
// a copy).
Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
-
+
// The high part is obtained by SRA'ing all but one of the bits of the lo
// part.
unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
// The low part is just a zero extension of the input (which degenerates to
// a copy).
Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
-
+
// The high part is just a zero.
Hi = DAG.getConstant(0, NVT);
break;
Lo = ExpandLibCall("__lshrdi3", Node, Hi);
break;
- case ISD::ADD:
+ case ISD::ADD:
ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
Lo, Hi);
break;
//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This implements the SelectionDAG class.
if (isa<ConstantSDNode>(N.Val)) return true;
if (isa<SetCCSDNode>(N.Val) && N.Val->hasOneUse())
return true;
- return false;
+ return false;
}
if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
// Cannot fold a signed integer setcc with an unsigned integer setcc.
return ISD::SETCC_INVALID;
-
+
unsigned Op = Op1 | Op2; // Combine all of the condition bits.
-
+
// If the N and U bits get set then the resultant comparison DOES suddenly
// care about orderedness, and is true when ordered.
if (Op > ISD::SETTRUE2)
bool isInteger) {
if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
// Cannot fold a signed setcc with an unsigned setcc.
- return ISD::SETCC_INVALID;
+ return ISD::SETCC_INVALID;
// Combine all of the condition bits.
return ISD::CondCode(Op1 & Op2);
// Now that we removed this operand, see if there are no uses of it left.
DeleteNodeIfDead(O, NodeSet);
}
-
+
// Remove the node from the nodes set and delete it.
std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet;
AllNodeSet.erase(N);
// Mask out any bits that are not valid for this constant.
if (VT != MVT::i64)
Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1;
-
+
SDNode *&N = Constants[std::make_pair(Val, VT)];
if (N) return SDOperand(N, 0);
N = new ConstantSDNode(Val, VT);
double DV;
uint64_t IV;
};
-
+
DV = Val;
SDNode *&N = ConstantFPs[std::make_pair(IV, VT)];
uint64_t C2 = N2C->getValue();
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
uint64_t C1 = N1C->getValue();
-
+
// Sign extend the operands if required
if (ISD::isSignedIntSetCC(Cond)) {
C1 = N1C->getSignExtended();
N2 = getConstant(C2, N2.getValueType());
N2C = cast<ConstantSDNode>(N2.Val);
}
-
+
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal)
return getConstant(0, VT); // X < MIN --> false
-
+
// Canonicalize setgt X, Min --> setne X, Min
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal)
return getSetCC(ISD::SETNE, VT, N1, N2);
-
+
// If we have setult X, 1, turn it into seteq X, 0
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1)
return getSetCC(ISD::SETEQ, VT, N1,
if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val))
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
double C1 = N1C->getValue(), C2 = N2C->getValue();
-
+
switch (Cond) {
default: break; // FIXME: Implement the rest of these!
case ISD::SETEQ: return getConstant(C1 == C2, VT);
}
// FIXME: move this stuff to the DAG Combiner when it exists!
-
+
// Simplify (X+Z) == X --> Z == 0
if (N1.getOperand(0) == N2)
return getSetCC(Cond, VT, N1.getOperand(1),
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
// (Z-X) == X --> Z == X<<1
return getSetCC(Cond, VT, N1.getOperand(0),
- getNode(ISD::SHL, N2.getValueType(),
+ getNode(ISD::SHL, N2.getValueType(),
N2, getConstant(1, TLI.getShiftAmountTy())));
}
}
const TargetLowering &TLI) {
unsigned SrcBits;
if (Mask == 0) return true;
-
+
// If we know the result of a setcc has the top bits zero, use this info.
switch (Op.getOpcode()) {
case ISD::UNDEF:
return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
case ISD::SETCC:
- return ((Mask & 1) == 0) &&
+ return ((Mask & 1) == 0) &&
TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
case ISD::ZEXTLOAD:
Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) {
if ((Op2 == ISD::SETEQ && Opcode == ISD::AND) ||
(Op2 == ISD::SETNE && Opcode == ISD::OR))
- return getSetCC(Op2, VT,
+ return getSetCC(Op2, VT,
getNode(ISD::OR, LR.getValueType(), LL, RL), LR);
}
Op2 = ISD::getSetCCSwappedOperands(Op2);
goto MatchedBackwards;
}
-
+
if (LL == RL && LR == RR) {
MatchedBackwards:
ISD::CondCode Result;
if (N1C)
if (N1C->getValue())
return N2; // select true, X, Y -> X
- else
+ else
return N3; // select false, X, Y -> Y
if (N2 == N3) return N2; // select C, X, X -> X
SDNode *N = new SDNode(Opcode, N1, N2, N3);
switch (Opcode) {
- default:
+ default:
N->setValueTypes(VT);
break;
case ISD::DYNAMIC_STACKALLOC: // DYNAMIC_STACKALLOC produces pointer and chain
// If we are extending the result of a setcc, and we already know the
// contents of the top bits, eliminate the extension.
if (N1.getOpcode() == ISD::SETCC &&
- TLI.getSetCCResultContents() ==
+ TLI.getSetCCResultContents() ==
TargetLowering::ZeroOrNegativeOneSetCCResult)
return N1;
if (VT == EVT)
return getNode(ISD::LOAD, VT, N1, N2);
assert(EVT < VT && "Should only be an extending load, not truncating!");
- assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) &&
+ assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) &&
"Cannot sign/zero extend a FP load!");
assert(MVT::isInteger(VT) == MVT::isInteger(EVT) &&
"Cannot convert from FP to Int or Int -> FP!");
if (isa<Constant>(N1)) {
SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1);
if (isa<Constant>(Op))
- N1 = Op;
+ N1 = Op;
}
// Also for ConstantFP?
#endif
case ISD::SETOLT: return "setcc:setolt";
case ISD::SETOLE: return "setcc:setole";
case ISD::SETONE: return "setcc:setone";
-
- case ISD::SETO: return "setcc:seto";
+
+ case ISD::SETO: return "setcc:seto";
case ISD::SETUO: return "setcc:setuo";
case ISD::SETUEQ: return "setcc:setue";
case ISD::SETUGT: return "setcc:setugt";
case ISD::SETULT: return "setcc:setult";
case ISD::SETULE: return "setcc:setule";
case ISD::SETUNE: return "setcc:setune";
-
+
case ISD::SETEQ: return "setcc:seteq";
case ISD::SETGT: return "setcc:setgt";
case ISD::SETGE: return "setcc:setge";
std::cerr << "<" << CSDN->getValue() << ">";
} else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
std::cerr << "<" << CSDN->getValue() << ">";
- } else if (const GlobalAddressSDNode *GADN =
+ } else if (const GlobalAddressSDNode *GADN =
dyn_cast<GlobalAddressSDNode>(this)) {
std::cerr << "<";
WriteAsOperand(std::cerr, GADN->getGlobal()) << ">";
std::cerr << "<" << FIDN->getIndex() << ">";
} else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
std::cerr << "<" << CP->getIndex() << ">";
- } else if (const BasicBlockSDNode *BBDN =
+ } else if (const BasicBlockSDNode *BBDN =
dyn_cast<BasicBlockSDNode>(this)) {
std::cerr << "<";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
else
std::cerr << "\n" << std::string(indent+2, ' ')
<< (void*)N->getOperand(i).Val << ": <multiple use>";
-
+
std::cerr << "\n" << std::string(indent, ' ');
N->dump();
//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This implements the SelectionDAGISel class.
unsigned MakeReg(MVT::ValueType VT) {
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
}
-
+
unsigned CreateRegForValue(const Value *V) {
MVT::ValueType VT = TLI.getValueType(V->getType());
// The common case is that we will only create one register for this
// If we are promoting this value, pick the next largest supported type.
return MakeReg(TLI.getTypeToTransformTo(VT));
}
-
+
// If this value is represented with multiple target registers, make sure
// to create enough consequtive registers of the right (smaller) type.
unsigned NT = VT-1; // Find the type to use.
while (TLI.getNumElements((MVT::ValueType)NT) != 1)
--NT;
-
+
unsigned R = MakeReg((MVT::ValueType)NT);
for (unsigned i = 1; i != NV; ++i)
MakeReg((MVT::ValueType)NT);
return R;
}
-
+
unsigned InitializeRegForValue(const Value *V) {
unsigned &R = ValueMap[V];
assert(R == 0 && "Already initialized this value register!");
}
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
- Function &fn, MachineFunction &mf)
+ Function &fn, MachineFunction &mf)
: TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
// Initialize the mapping of values to registers. This is only set up for
FunctionLoweringInfo &FuncInfo;
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
- FunctionLoweringInfo &funcinfo)
+ FunctionLoweringInfo &funcinfo)
: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
FuncInfo(funcinfo) {
}
SDOperand getRoot() {
if (PendingLoads.empty())
return DAG.getRoot();
-
+
if (PendingLoads.size() == 1) {
SDOperand Root = PendingLoads[0];
DAG.setRoot(Root);
IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
-
+
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
}
}
void SelectionDAGLowering::visitLoad(LoadInst &I) {
SDOperand Ptr = getValue(I.getOperand(0));
-
+
SDOperand Root;
if (I.isVolatile())
Root = getRoot();
case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
-
+
case Intrinsic::isunordered:
setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1,getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
return;
}
}
-
+
SDOperand Callee;
if (!RenameFn)
Callee = getValue(I.getOperand(0));
else
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
std::vector<std::pair<SDOperand, const Type*> > Args;
-
+
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
Value *Arg = I.getOperand(i);
SDOperand ArgNode = getValue(Arg);
Args.push_back(std::make_pair(ArgNode, Arg->getType()));
}
-
+
const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
-
+
std::pair<SDOperand,SDOperand> Result =
TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), Callee, Args, DAG);
if (I.getType() != Type::VoidTy)
Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerCallTo(getRoot(), I.getType(), false,
+ TLI.LowerCallTo(getRoot(), I.getType(), false,
DAG.getExternalSymbol("malloc", IntPtr),
Args, DAG);
setValue(&I, Result.first); // Pointers always fit in registers
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
+ TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
I.getType(), DAG);
setValue(&I, Result.first);
DAG.setRoot(Result.second);
void SelectionDAGLowering::visitVANext(VANextInst &I) {
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
+ TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
I.getArgType(), DAG);
setValue(&I, Result.first);
DAG.setRoot(Result.second);
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
SelectBasicBlock(I, MF, FuncInfo);
-
+
return true;
}
AI != E; ++AI,++a)
if (!AI->use_empty()) {
SDL.setValue(AI, Args[a]);
- SDOperand Copy =
+ SDOperand Copy =
CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
UnorderedChains.push_back(Copy);
}
std::make_pair(AI, a)));
} else {
SDL.setValue(AI, Args[a]);
- SDOperand Copy =
+ SDOperand Copy =
CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
UnorderedChains.push_back(Copy);
}
if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) {
// Lower the arguments into this block.
std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
-
+
// Set up the value mapping for the local arguments.
for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB;
++BLAI)
SDL.setValue(BLAI->second.first, Args[BLAI->second.second]);
-
+
// Any dead arguments will just be ignored here.
}
}
SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
std::vector<SDOperand> UnorderedChains;
-
+
// Lower any arguments needed in this block.
LowerArguments(LLVMBB, SDL, UnorderedChains);
// directly add them, because expansion might result in multiple MBB's for one
// BB. As such, the start of the BB might correspond to a different MBB than
// the end.
- //
+ //
// Emit constants only once even if used by multiple PHI nodes.
std::map<Constant*, unsigned> ConstantsOut;
} else {
Reg = FuncInfo.ValueMap[PHIOp];
if (Reg == 0) {
- assert(isa<AllocaInst>(PHIOp) &&
+ assert(isa<AllocaInst>(PHIOp) &&
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
"Didn't codegen value into a register!??");
Reg = FuncInfo.CreateRegForValue(PHIOp);
CopyValueToVirtualRegister(SDL, PHIOp, Reg));
}
}
-
+
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
unsigned NumElements =
//===-- SelectionDAGPrinter.cpp - Implement SelectionDAG::viewGraph() -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This implements the SelectionDAG::viewGraph method.
Op += ": " + utostr(CSDN->getValue());
} else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(Node)) {
Op += ": " + ftostr(CSDN->getValue());
- } else if (const GlobalAddressSDNode *GADN =
+ } else if (const GlobalAddressSDNode *GADN =
dyn_cast<GlobalAddressSDNode>(Node)) {
Op += ": " + GADN->getGlobal()->getName();
} else if (const FrameIndexSDNode *FIDN =
Op += " " + itostr(FIDN->getIndex());
} else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Node)){
Op += "<" + utostr(CP->getIndex()) + ">";
- } else if (const BasicBlockSDNode *BBDN =
+ } else if (const BasicBlockSDNode *BBDN =
dyn_cast<BasicBlockSDNode>(Node)) {
Op = "BB: ";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
}
return Op;
}
-
+
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
/// rendered using 'dot'.
bool runOnMachineFunction(MachineFunction&);
};
- RegisterPass<TwoAddressInstructionPass>
+ RegisterPass<TwoAddressInstructionPass>
X("twoaddressinstruction", "Two-Address instruction pass");
};
mbbi->insert(mi, NewMI); // Insert the new inst
mbbi->erase(mi); // Nuke the old inst.
mi = NewMI;
- }
+ }
++NumCommuted;
regB = regC;
}
}
// If this instruction is potentially convertible to a true
- // three-address instruction,
+ // three-address instruction,
if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
// replace all occurences of regB with regA
for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
- if (mi->getOperand(i).isRegister() &&
+ if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB)
mi->SetMachineOperandReg(i, regA);
}
//===-- UnreachableBlockElim.cpp - Remove unreachable blocks for codegen --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This pass is an extremely simple version of the SimplifyCFG pass. Its sole
// job is to delete LLVM basic blocks that are not reachable from the entry
// node. To do this, it performs a simple depth first traversal of the CFG,
unsigned OpNo, MachineInstr *NewMI) {
// Move previous memory references folded to new instruction.
MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
- for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
+ for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
MI2VirtMap.erase(I++);
e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
-
+
}
for (unsigned i = MRegisterInfo::FirstVirtualRegister,
unsigned PhysReg = VRM.getPhys(VirtReg);
if (VRM.hasStackSlot(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg);
-
+
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
++NumLoads;
DEBUG(std::cerr << '\t' << *prior(MII));
}
-
+
if (MO.isDef()) {
MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
++NumStores;
struct ReusedOp {
// The MachineInstr operand that reused an available value.
unsigned Operand;
-
+
// StackSlot - The spill slot of the value being reused.
unsigned StackSlot;
-
+
// PhysRegReused - The physical register the value was available in.
unsigned PhysRegReused;
-
+
// AssignedPhysReg - The physreg that was assigned for use by the reload.
unsigned AssignedPhysReg;
-
+
ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr)
: Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {}
};
// Okay, we found out that an alias of a reused register
// was used. This isn't good because it means we have
// to undo a previous reuse.
- MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
+ MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
Op.StackSlot);
ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
PhysRegsAvailable);
break;
}
}
-
+
if (!OpTakenCareOf) {
ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable);
TakenCareOf = true;
}
- }
+ }
if (!TakenCareOf) {
// The only vregs left are stack slot definitions.
/// instructions, we need to know which virtual register was
/// read/written by this instruction.
MI2VirtMapTy MI2VirtMap;
-
+
VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
//===-- Debugger.cpp - LLVM debugger library implementation ---------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file contains the main implementation of the LLVM debugger library.
//
//===----------------------------------------------------------------------===//
} catch (const char *) {
} catch (const std::string &) {
}
-
+
unloadProgram();
}
try {
std::auto_ptr<ModuleProvider> Result(getBytecodeModuleProvider(Filename));
if (!Result.get()) return 0;
-
+
Result->materializeModule();
return Result.release()->releaseModule();
} catch (...) {
// Don't trust the current frame: get the caller frame.
void *ParentFrame = Process->getPreviousFrame(CurrentFrame);
-
+
// Ok, we have some information, run the program one step.
Process->stepProgram();
//===- lib/Debugger/FDHandle.cpp - File Descriptor Handle -----------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements a class for ensuring that Unix file handles get closed.
//
FDHandle::~FDHandle() throw() {
- if (FD != -1)
+ if (FD != -1)
::close(FD);
}
FDHandle &FDHandle::operator=(int fd) throw() {
- if (FD != -1)
+ if (FD != -1)
::close(FD);
FD = fd;
return *this;
//===- lib/Debugger/FDHandle.h - File Descriptor Handle ---------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a family of utility functions which are useful for doing
//===-- ProgramInfo.cpp - Compute and cache info about a program ----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the ProgramInfo and related classes, by sorting through
// the loaded Module.
//
if (const ConstantInt *C = dyn_cast<ConstantInt>(CI->getOperand(3)))
CurColNo = C->getRawValue();
const Value *Op = CI->getOperand(4);
-
+
if ((CurDesc = dyn_cast<GlobalVariable>(Op)) &&
(LineNo < LastLineNo ||
(LineNo == LastLineNo && ColNo < LastColNo))) {
LastDesc = CurDesc;
LastLineNo = CurLineNo;
- LastColNo = CurColNo;
+ LastColNo = CurColNo;
}
ShouldRecurse = false;
}
if (LineNo < LastLineNo || (LineNo == LastLineNo && ColNo < LastColNo)){
LastDesc = GV;
LastLineNo = CurLineNo;
- LastColNo = CurColNo;
+ LastColNo = CurColNo;
}
}
}
}
-
+
if (LastDesc) {
LineNo = LastLineNo != ~0U ? LastLineNo : 0;
ColNo = LastColNo != ~0U ? LastColNo : 0;
if (CS->getNumOperands() > 4) {
if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(CS->getOperand(1)))
Version = CUI->getValue();
-
+
BaseName = getStringValue(CS->getOperand(3));
Directory = getStringValue(CS->getOperand(4));
}
if (ConstantStruct *CS = dyn_cast<ConstantStruct>(Desc->getInitializer()))
if (CS->getNumOperands() > 2) {
// Entry #1 is the file descriptor.
- if (const GlobalVariable *GV =
+ if (const GlobalVariable *GV =
dyn_cast<GlobalVariable>(CS->getOperand(1)))
SourceFile = &PI.getSourceFile(GV);
std::multimap<std::string, SourceFileInfo*>::const_iterator Start, End;
getSourceFiles();
tie(Start, End) = SourceFileIndex.equal_range(Filename);
-
+
if (Start == End) throw "Could not find source file '" + Filename + "'!";
const SourceFileInfo &SFI = *Start->second;
++Start;
//===-- RuntimeInfo.cpp - Compute and cache info about running program ----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the RuntimeInfo and related classes, by querying and
// cachine information from the running inferior process.
//
: RI(ri), SourceInfo(0) {
FrameID = RI.getInferiorProcess().getPreviousFrame(ParentFrameID);
if (FrameID == 0) throw "Stack frame does not exist!";
-
+
// Compute lazily as needed.
FunctionDesc = 0;
}
//===-- SourceFile.cpp - SourceFile implementation for the debugger -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the SourceFile class for the LLVM debugger.
//
//===----------------------------------------------------------------------===//
using namespace llvm;
-/// readFile - Load Filename
+/// readFile - Load Filename
///
void SourceFile::readFile() {
File.map();
//===-- SourceLanguage-CFamily.cpp - C family SourceLanguage impl ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the SourceLanguage class for the C family of languages
// (K&R C, C89, C99, etc).
//
//===-- SourceLanguage-CPlusPlus.cpp - C++ SourceLanguage impl ------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the SourceLanguage class for the C++ language.
//
//===----------------------------------------------------------------------===//
//===-- SourceLanguage-Unknown.cpp - Implement itf for unknown languages --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// If the LLVM debugger does not have a module for a particular language, it
// falls back on using this one to perform the source-language interface. This
// interface is not wonderful, but it gets the job done.
//===-- SourceLanguage.cpp - Implement the SourceLanguage class -----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the SourceLanguage class.
//
//===----------------------------------------------------------------------===//
//===-- UnixLocalInferiorProcess.cpp - A Local process on a Unixy system --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file provides one implementation of the InferiorProcess class, which is
// designed to be used on unixy systems (those that support pipe, fork, exec,
// and signals).
// FinishProgram: FrameDesc*->char - This command causes the program to
// continue execution until the specified function frame returns.
- FinishProgram,
+ FinishProgram,
// ContProgram: void->char - This command causes the program to continue
// execution, stopping at some point in the future.
// Start the child running...
startChild(M, Arguments, envp);
-
+
// Okay, we created the program and it is off and running. Wait for it to
// stop now.
try {
/// getFrameLocation - This method returns the source location where each stack
/// frame is stopped.
-void IP::getFrameLocation(void *Frame, unsigned &LineNo, unsigned &ColNo,
+void IP::getFrameLocation(void *Frame, unsigned &LineNo, unsigned &ColNo,
const GlobalVariable *&SourceDesc) const {
sendCommand(GetFrameLocation, &Frame, sizeof(Frame));
LocationToken Loc;
/// died, otherwise it just returns the exit code if it had to be killed.
void IP::killChild() const {
assert(ChildPID != 0 && "Child has already been reaped!");
-
+
// If the process terminated on its own accord, closing the pipe file
// descriptors, we will get here. Check to see if the process has already
// died in this manner, gracefully.
throw InferiorProcessDead(WTERMSIG(Status));
throw InferiorProcessDead(-1);
}
-
+
// Otherwise, the child exists and has not yet been killed.
if (kill(ChildPID, SIGKILL) < 0)
throw "Error killing child process!";
ExecutionEngine::create(new ExistingModuleProvider(M), false,
new DebuggerIntrinsicLowering());
assert(EE && "Couldn't create an ExecutionEngine, not even an interpreter?");
-
+
// Call the main function from M as if its signature were:
// int main (int argc, char **argv, const char **envp)
// using the contents of Args to determine argc & argv, and the contents of
//===-- ExecutionEngine.cpp - Common Implementation shared by EEs ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file defines the common interface used by the various execution engine
// subclasses.
//
Statistic<> NumGlobals ("lli", "Number of global vars initialized");
}
-ExecutionEngine::ExecutionEngine(ModuleProvider *P) :
+ExecutionEngine::ExecutionEngine(ModuleProvider *P) :
CurMod(*P->getModule()), MP(P) {
assert(P && "ModuleProvider is null?");
}
const GlobalValue *ExecutionEngine::getGlobalValueAtAddress(void *Addr) {
// If we haven't computed the reverse mapping yet, do so first.
if (GlobalAddressReverseMap.empty()) {
- for (std::map<const GlobalValue*, void *>::iterator I =
+ for (std::map<const GlobalValue*, void *>::iterator I =
GlobalAddressMap.begin(), E = GlobalAddressMap.end(); I != E; ++I)
GlobalAddressReverseMap.insert(std::make_pair(I->second, I->first));
}
unsigned Size = InputArgv[i].size()+1;
char *Dest = new char[Size];
DEBUG(std::cerr << "ARGV[" << i << "] = " << (void*)Dest << "\n");
-
+
std::copy(InputArgv[i].begin(), InputArgv[i].end(), Dest);
Dest[Size-1] = 0;
-
+
// Endian safe: Result[i] = (PointerTy)Dest;
EE->StoreValueToMemory(PTOGV(Dest), (GenericValue*)(Result+i*PtrSize),
SBytePtr);
/// If possible, create a JIT, unless the caller specifically requests an
/// Interpreter or there's an error. If even an Interpreter cannot be created,
-/// NULL is returned.
+/// NULL is returned.
///
-ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
+ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
bool ForceInterpreter,
IntrinsicLowering *IL) {
ExecutionEngine *EE = 0;
}
}
- if (EE == 0)
+ if (EE == 0)
delete IL;
else
- // Make sure we can resolve symbols in the program as well. The zero arg
+ // Make sure we can resolve symbols in the program as well. The zero arg
// to the function tells DynamicLibrary to load the program, not a library.
sys::DynamicLibrary::LoadLibraryPermanently(0);
}
/// FIXME: document
-///
+///
GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
GenericValue Result;
if (isa<UndefValue>(C)) return Result;
std::vector<Value*> Indexes(CE->op_begin()+1, CE->op_end());
uint64_t Offset =
TD->getIndexedOffset(CE->getOperand(0)->getType(), Indexes);
-
+
Result.LongVal += Offset;
return Result;
}
// Handle a cast of pointer to any integral type...
if (isa<PointerType>(Op->getType()) && C->getType()->isIntegral())
return GV;
-
+
// Handle cast of integer to a pointer...
if (isa<PointerType>(C->getType()) && Op->getType()->isIntegral())
switch (Op->getType()->getTypeID()) {
std::cerr << "ConstantExpr not handled as global var init: " << *CE << "\n";
abort();
}
-
+
switch (C->getType()->getTypeID()) {
#define GET_CONST_VAL(TY, CTY, CLASS) \
case Type::TY##TyID: Result.TY##Val = (CTY)cast<CLASS>(C)->getValue(); break
case Type::DoubleTyID:
case Type::ULongTyID:
case Type::LongTyID:
- Ptr->Untyped[7] = (unsigned char)(Val.ULongVal );
+ Ptr->Untyped[7] = (unsigned char)(Val.ULongVal );
Ptr->Untyped[6] = (unsigned char)(Val.ULongVal >> 8);
Ptr->Untyped[5] = (unsigned char)(Val.ULongVal >> 16);
Ptr->Untyped[4] = (unsigned char)(Val.ULongVal >> 24);
case Type::ShortTyID: Result.UShortVal = (unsigned)Ptr->Untyped[0] |
((unsigned)Ptr->Untyped[1] << 8);
break;
- Load4BytesLittleEndian:
+ Load4BytesLittleEndian:
case Type::FloatTyID:
case Type::UIntTyID:
case Type::IntTyID: Result.UIntVal = (unsigned)Ptr->Untyped[0] |
switch (Init->getType()->getTypeID()) {
case Type::ArrayTyID: {
const ConstantArray *CPA = cast<ConstantArray>(Init);
- unsigned ElementSize =
+ unsigned ElementSize =
getTargetData().getTypeSize(cast<ArrayType>(CPA->getType())->getElementType());
for (unsigned i = 0, e = CPA->getNumOperands(); i != e; ++i)
InitializeMemory(CPA->getOperand(i), (char*)Addr+i*ElementSize);
///
void ExecutionEngine::emitGlobals() {
const TargetData &TD = getTargetData();
-
+
// Loop over all of the global variables in the program, allocating the memory
// to hold them.
for (Module::const_global_iterator I = getModule().global_begin(), E = getModule().global_end();
if (!I->isExternal()) {
// Get the type of the global...
const Type *Ty = I->getType()->getElementType();
-
+
// Allocate some memory for it!
unsigned Size = TD.getTypeSize(Ty);
addGlobalMapping(I, new char[Size]);
abort();
}
}
-
+
// Now that all of the globals are set up in memory, loop through them all and
// initialize their contents.
for (Module::const_global_iterator I = getModule().global_begin(), E = getModule().global_end();
//===-- ValueTypes.cpp - Implementation of MVT::ValueType methods ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements methods in the CodeGen/ValueTypes.h header.
projects / oota-llvm.git / commitdiff