--- /dev/null
+/*\r
+ * Driver for RK-UART controller.\r
+ * Based on drivers/tty/serial/8250.c\r
+ *\r
+ * Copyright (C) 2011 Rochchip.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+\r
+ * (at your option) any later version.\r
+ *\r
+ * Author: hhb@rock-chips.com\r
+ * Date: 2011.06.18\r
+ */\r
+\r
+#ifndef CONFIG_SERIAL_RK_CONSOLE\r
+#if defined(CONFIG_SERIAL_RK29_CONSOLE_STANDAR) || defined(CONFIG_SERIAL_RK29_CONSOLE)\r
+#define CONFIG_SERIAL_RK_CONSOLE\r
+#endif\r
+#endif\r
+\r
+#if defined(CONFIG_SERIAL_RK_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)\r
+#define SUPPORT_SYSRQ\r
+#endif\r
+\r
+//#define DEBUG\r
+#include <linux/module.h>\r
+#include <linux/ioport.h>\r
+#include <linux/init.h>\r
+#include <linux/console.h>\r
+#include <linux/sysrq.h>\r
+#include <linux/delay.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/tty.h>\r
+#include <linux/ratelimit.h>\r
+#include <linux/tty_flip.h>\r
+#include <linux/serial_reg.h>\r
+#include <linux/serial_core.h>\r
+#include <linux/serial.h>\r
+#include <linux/serial_8250.h>\r
+#include <linux/nmi.h>\r
+#include <linux/mutex.h>\r
+#include <linux/slab.h>\r
+#include <linux/clk.h>\r
+#include <linux/timer.h>\r
+#include <linux/workqueue.h>\r
+#include <mach/rk29-dma-pl330.h>\r
+#include <linux/dma-mapping.h>\r
+\r
+#include <asm/io.h>\r
+#include <asm/irq.h>\r
+\r
+\r
+#define PORT_RK 90\r
+#define UART_USR 0x1F /* UART Status Register */\r
+#define UART_IER_PTIME 0x80 /* Programmable THRE Interrupt Mode Enable */\r
+#define RX_TIMEOUT (3000*10) //uint ms\r
+\r
+#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)\r
+\r
+#define UART_NR 4 //uart port number\r
+\r
+/* configurate whether the port transmit-receive by DMA */\r
+#define OPEN_DMA 1\r
+#define CLOSE_DMA 0\r
+\r
+#ifdef CONFIG_UART0_DMA_RK29\r
+#define UART0_USE_DMA OPEN_DMA\r
+#else\r
+#define UART0_USE_DMA CLOSE_DMA\r
+#endif\r
+\r
+#ifdef CONFIG_UART2_DMA_RK29\r
+#define UART2_USE_DMA OPEN_DMA\r
+#else\r
+#define UART2_USE_DMA CLOSE_DMA\r
+#endif\r
+\r
+#ifdef CONFIG_UART3_DMA_RK29\r
+#define UART3_USE_DMA OPEN_DMA\r
+#else\r
+#define UART3_USE_DMA CLOSE_DMA\r
+#endif\r
+\r
+#define UART1_USE_DMA CLOSE_DMA\r
+\r
+#define DMA_TX_TRRIGE_LEVEL 30\r
+\r
+#define USE_TIMER 1 // use timer for dma transport\r
+#define THRE_MODE 0X00 //0yhh\r
+\r
+static struct uart_driver serial_rk_reg;\r
+\r
+/*\r
+ * Debugging.\r
+ */\r
+#define DBG_PORT 1\r
+#ifdef CONFIG_SERIAL_CORE_CONSOLE\r
+#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)\r
+#else\r
+#define uart_console(port) (0)\r
+#endif\r
+\r
+#ifdef DEBUG\r
+extern void printascii(const char *);\r
+\r
+static void dbg(const char *fmt, ...)\r
+{\r
+ va_list va;\r
+ char buff[256];\r
+\r
+ va_start(va, fmt);\r
+ vsprintf(buff, fmt, va);\r
+ va_end(va);\r
+\r
+ printascii(buff);\r
+}\r
+\r
+#define DEBUG_INTR(fmt...) if (!uart_console(&up->port)) dbg(fmt)\r
+#else\r
+#define DEBUG_INTR(fmt...) do { } while (0)\r
+#endif\r
+\r
+\r
+/* added by hhb@rock-chips.com for uart dma transfer */\r
+\r
+struct rk29_uart_dma_t {\r
+ u32 use_dma; //1:used\r
+ u32 rx_dma_start;\r
+ enum dma_ch rx_dmach;\r
+ enum dma_ch tx_dmach;\r
+ u32 tx_dma_inited;\r
+ u32 rx_dma_inited;\r
+ spinlock_t tx_lock;\r
+ spinlock_t rx_lock;\r
+ char * rx_buffer;\r
+ char * tx_buffer;\r
+ dma_addr_t rx_phy_addr;\r
+ dma_addr_t tx_phy_addr;\r
+ u32 rx_buffer_size;\r
+ u32 tx_buffer_size;\r
+\r
+ u32 rb_cur_pos;\r
+ u32 rb_pre_pos;\r
+ u32 rx_size;\r
+ char use_timer;\r
+ char tx_dma_used;\r
+ /* timer to poll activity on rx dma */\r
+ struct timer_list rx_timer;\r
+ int rx_timeout;\r
+\r
+};\r
+\r
+struct uart_rk_port {\r
+ struct uart_port port;\r
+ struct platform_device *pdev;\r
+ struct clk *clk;\r
+ unsigned int tx_loadsz; /* transmit fifo load size */\r
+ unsigned char ier;\r
+ unsigned char lcr;\r
+ unsigned char mcr;\r
+ unsigned char iir;\r
+\r
+ /*\r
+ * Some bits in registers are cleared on a read, so they must\r
+ * be saved whenever the register is read but the bits will not\r
+ * be immediately processed.\r
+ */\r
+#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS\r
+ unsigned char lsr_saved_flags;\r
+#if 0\r
+#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA\r
+ unsigned char msr_saved_flags;\r
+#endif\r
+\r
+ char name[12];\r
+ char fifo[32];\r
+ char fifo_size;\r
+ unsigned long port_activity;\r
+ struct work_struct uart_work;\r
+ struct work_struct uart_work_rx;\r
+ struct workqueue_struct *uart_wq;\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t;\r
+};\r
+\r
+static void serial_rk_release_dma_tx(struct uart_port *port);\r
+static int serial_rk_start_tx_dma(struct uart_port *port);\r
+static void serial_rk_rx_timeout(unsigned long uart);\r
+static void serial_rk_release_dma_rx(struct uart_port *port);\r
+static int serial_rk_start_rx_dma(struct uart_port *port);\r
+static int serial_rk_startup(struct uart_port *port);\r
+static inline unsigned int serial_in(struct uart_rk_port *up, int offset)\r
+{\r
+ offset = offset << 2;\r
+ return readb(up->port.membase + offset);\r
+}\r
+\r
+/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */\r
+static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,\r
+ unsigned char value)\r
+{\r
+ if (offset == UART_LCR)\r
+ up->lcr = value;\r
+}\r
+\r
+/* Read the IER to ensure any interrupt is cleared before returning from ISR. */\r
+static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)\r
+{\r
+ if (offset == UART_TX || offset == UART_IER)\r
+ serial_in(up, UART_IER);\r
+}\r
+\r
+static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)\r
+{\r
+ dwapb_save_out_value(up, offset, value);\r
+ writeb(value, up->port.membase + (offset << 2));\r
+ dwapb_check_clear_ier(up, offset);\r
+}\r
+\r
+/* Uart divisor latch read */\r
+static inline int serial_dl_read(struct uart_rk_port *up)\r
+{\r
+ return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;\r
+}\r
+\r
+/* Uart divisor latch write */\r
+static inline void serial_dl_write(struct uart_rk_port *up, unsigned int value)\r
+{\r
+ serial_out(up, UART_DLL, value & 0xff);\r
+ serial_out(up, UART_DLM, value >> 8 & 0xff);\r
+}\r
+\r
+static void serial_lcr_write(struct uart_rk_port *up, unsigned char value)\r
+{\r
+ unsigned int tmout = 10000;\r
+\r
+ for (;;) {\r
+ unsigned char lcr;\r
+ serial_out(up, UART_LCR, value);\r
+ lcr = serial_in(up, UART_LCR);\r
+ if (lcr == value)\r
+ break;\r
+ /* Read the USR to clear any busy interrupts */\r
+ serial_in(up, UART_USR);\r
+ serial_in(up, UART_RX);\r
+ if (--tmout == 0)\r
+ break;\r
+ udelay(1);\r
+ }\r
+}\r
+\r
+static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)\r
+{\r
+ if (!(up->ier & UART_IER_THRI)) {\r
+ up->ier |= UART_IER_THRI;\r
+ serial_out(up, UART_IER, up->ier);\r
+ }\r
+}\r
+\r
+\r
+static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)\r
+{\r
+ if (up->ier & UART_IER_THRI) {\r
+ up->ier &= ~UART_IER_THRI;\r
+ serial_out(up, UART_IER, up->ier);\r
+ }\r
+}\r
+\r
+/*\r
+ * FIFO support.\r
+ */\r
+static void serial_rk_clear_fifos(struct uart_rk_port *up)\r
+{\r
+ serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);\r
+ serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |\r
+ UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);\r
+ serial_out(up, UART_FCR, 0);\r
+}\r
+\r
+static inline void __stop_tx(struct uart_rk_port *p)\r
+{\r
+ if (p->ier & UART_IER_THRI) {\r
+ p->ier &= ~UART_IER_THRI;\r
+ serial_out(p, UART_IER, p->ier);\r
+ }\r
+}\r
+\r
+static void serial_rk_stop_tx(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+\r
+ if(OPEN_DMA == prk29_uart_dma_t->use_dma){\r
+ serial_rk_release_dma_tx(port);\r
+ }\r
+ __stop_tx(up);\r
+}\r
+\r
+\r
+static void serial_rk_start_tx(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+/*\r
+ * struct circ_buf *xmit = &port->state->xmit;\r
+ int size = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);\r
+ if(size > 64){\r
+ serial_rk_start_tx_dma(port);\r
+ }\r
+ else{\r
+ serial_rk_enable_ier_thri(up);\r
+ }\r
+*/\r
+\r
+ if(0 == serial_rk_start_tx_dma(port)){\r
+ serial_rk_enable_ier_thri(up);\r
+ }\r
+\r
+}\r
+\r
+\r
+static void serial_rk_stop_rx(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+\r
+ if(OPEN_DMA == prk29_uart_dma_t->use_dma){\r
+ serial_rk_release_dma_rx(port);\r
+ }\r
+ up->ier &= ~UART_IER_RLSI;\r
+ up->port.read_status_mask &= ~UART_LSR_DR;\r
+ serial_out(up, UART_IER, up->ier);\r
+}\r
+\r
+\r
+static void serial_rk_enable_ms(struct uart_port *port)\r
+{\r
+ /* no MSR capabilities */\r
+#if 0\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+ up->ier |= UART_IER_MSI;\r
+ serial_out(up, UART_IER, up->ier);\r
+#endif\r
+}\r
+\r
+\r
+/*\r
+ * Start transmitting by dma.\r
+ */\r
+#define DMA_SERIAL_BUFFER_SIZE UART_XMIT_SIZE\r
+\r
+/* added by hhb@rock-chips.com for uart dma transfer*/\r
+static struct rk29_uart_dma_t rk29_uart_ports_dma_t[] = {\r
+ {UART0_USE_DMA, 0, DMACH_UART0_RX, DMACH_UART0_TX},\r
+ {UART1_USE_DMA, 0, DMACH_UART1_RX, DMACH_UART1_TX},\r
+ {UART2_USE_DMA, 0, DMACH_UART2_RX, DMACH_UART2_TX},\r
+ {UART3_USE_DMA, 0, DMACH_UART3_RX, DMACH_UART3_TX},\r
+};\r
+\r
+\r
+/* DMAC PL330 add by hhb@rock-chips.com */\r
+static struct rk29_dma_client rk29_uart_dma_client = {\r
+ .name = "rk29xx-uart-dma",\r
+};\r
+\r
+/*TX*/\r
+\r
+static void serial_rk_release_dma_tx(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+ if(!port){\r
+ return;\r
+ }\r
+ if(prk29_uart_dma_t && prk29_uart_dma_t->tx_dma_inited) {\r
+ rk29_dma_free(prk29_uart_dma_t->tx_dmach, &rk29_uart_dma_client);\r
+ prk29_uart_dma_t->tx_dma_inited = 0;\r
+ }\r
+}\r
+\r
+/*this function will be called every time after rk29_dma_enqueue() be invoked*/\r
+static void serial_rk_dma_txcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
+ struct uart_port *port = buf;\r
+ struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
+ struct circ_buf *xmit = &port->state->xmit;\r
+\r
+ if(result != RK29_RES_OK){\r
+ return;\r
+ }\r
+\r
+ port->icount.tx += size;\r
+ xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);\r
+\r
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
+ uart_write_wakeup(&up->port);\r
+ spin_lock(&(up->prk29_uart_dma_t->tx_lock));\r
+ up->prk29_uart_dma_t->tx_dma_used = 0;\r
+ spin_unlock(&(up->prk29_uart_dma_t->tx_lock));\r
+ if (!uart_circ_empty(xmit)) {\r
+ serial_rk_start_tx_dma(port);\r
+ }\r
+\r
+ up->port_activity = jiffies;\r
+// dev_info(up->port.dev, "s:%d\n", size);\r
+}\r
+\r
+static int serial_rk_init_dma_tx(struct uart_port *port) {\r
+\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+ if(!port || !prk29_uart_dma_t){\r
+ dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");\r
+ return -1;\r
+ }\r
+\r
+ if(prk29_uart_dma_t->tx_dma_inited) {\r
+ return 0;\r
+ }\r
+\r
+ if (rk29_dma_request(prk29_uart_dma_t->tx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
+ dev_info(up->port.dev, "rk29_dma_request tx fail\n");\r
+ return -1;\r
+ }\r
+\r
+ if (rk29_dma_set_buffdone_fn(prk29_uart_dma_t->tx_dmach, serial_rk_dma_txcb)) {\r
+ dev_info(up->port.dev, "rk29_dma_set_buffdone_fn tx fail\n");\r
+ return -1;\r
+ }\r
+ if (rk29_dma_devconfig(prk29_uart_dma_t->tx_dmach, RK29_DMASRC_MEM, (unsigned long)(port->iobase + UART_TX))) {\r
+ dev_info(up->port.dev, "rk29_dma_devconfig tx fail\n");\r
+ return -1;\r
+ }\r
+ if (rk29_dma_config(prk29_uart_dma_t->tx_dmach, 1, 1)) {\r
+ dev_info(up->port.dev, "rk29_dma_config tx fail\n");\r
+ return -1;\r
+ }\r
+\r
+ prk29_uart_dma_t->tx_dma_inited = 1;\r
+ dev_info(up->port.dev, "serial_rk_init_dma_tx sucess\n");\r
+ return 0;\r
+\r
+}\r
+\r
+static int serial_rk_start_tx_dma(struct uart_port *port)\r
+{\r
+\r
+ struct circ_buf *xmit = &port->state->xmit;\r
+ struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+\r
+ if(0 == prk29_uart_dma_t->use_dma){\r
+ return CLOSE_DMA;\r
+ }\r
+\r
+ if(-1 == serial_rk_init_dma_tx(port)){\r
+ goto err_out;\r
+ }\r
+\r
+ if (1 == prk29_uart_dma_t->tx_dma_used){\r
+ return 1;\r
+ }\r
+ if(!uart_circ_empty(xmit)){\r
+ if (rk29_dma_enqueue(prk29_uart_dma_t->tx_dmach, port,\r
+ prk29_uart_dma_t->tx_phy_addr + xmit->tail,\r
+ CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE))) {\r
+ goto err_out;\r
+ }\r
+ }\r
+ rk29_dma_ctrl(prk29_uart_dma_t->tx_dmach, RK29_DMAOP_START);\r
+ spin_lock(&(prk29_uart_dma_t->tx_lock));\r
+ up->prk29_uart_dma_t->tx_dma_used = 1;\r
+ spin_unlock(&(prk29_uart_dma_t->tx_lock));\r
+\r
+ return 1;\r
+err_out:\r
+ dev_info(up->port.dev, "-serial_rk_start_tx_dma-error-\n");\r
+ return -1;\r
+\r
+}\r
+\r
+\r
+\r
+/*RX*/\r
+static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
+\r
+// printk("^\n");\r
+\r
+}\r
+\r
+static void serial_rk_release_dma_rx(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+ if(!port){\r
+ return;\r
+ }\r
+ if(prk29_uart_dma_t && prk29_uart_dma_t->rx_dma_inited) {\r
+ del_timer(&prk29_uart_dma_t->rx_timer);\r
+ rk29_dma_free(prk29_uart_dma_t->rx_dmach, &rk29_uart_dma_client);\r
+ prk29_uart_dma_t->rb_pre_pos = 0;\r
+ prk29_uart_dma_t->rx_dma_inited = 0;\r
+ prk29_uart_dma_t->rx_dma_start = 0;\r
+ }\r
+}\r
+\r
+\r
+static int serial_rk_init_dma_rx(struct uart_port *port) {\r
+\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+ if(!port || !prk29_uart_dma_t){\r
+ dev_info(up->port.dev, "serial_rk_init_dma_rx: port fail\n");\r
+ return -1;\r
+ }\r
+ if(prk29_uart_dma_t->rx_dma_inited) {\r
+ return 0;\r
+ }\r
+\r
+ if (rk29_dma_request(prk29_uart_dma_t->rx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
+ dev_info(up->port.dev, "rk29_dma_request fail rx \n");\r
+ return -1;\r
+ }\r
+\r
+ if (rk29_dma_set_buffdone_fn(prk29_uart_dma_t->rx_dmach, serial_rk_dma_rxcb)) {\r
+ dev_info(up->port.dev, "rk29_dma_set_buffdone_fn rx fail\n");\r
+ return -1;\r
+ }\r
+ if (rk29_dma_devconfig(prk29_uart_dma_t->rx_dmach, RK29_DMASRC_HW, (unsigned long)(port->iobase + UART_RX))) {\r
+ dev_info(up->port.dev, "rk29_dma_devconfig rx fail\n");\r
+ return -1;\r
+ }\r
+\r
+ if (rk29_dma_config(prk29_uart_dma_t->rx_dmach, 1, 1)) {\r
+ dev_info(up->port.dev, "rk29_dma_config rx fail\n");\r
+ return -1;\r
+ }\r
+\r
+ rk29_dma_setflags(prk29_uart_dma_t->rx_dmach, RK29_DMAF_CIRCULAR);\r
+\r
+ prk29_uart_dma_t->rx_dma_inited = 1;\r
+ dev_info(up->port.dev, "serial_rk_init_dma_rx sucess\n");\r
+ return 0;\r
+\r
+}\r
+\r
+static int serial_rk_start_rx_dma(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+ if(0 == prk29_uart_dma_t->use_dma){\r
+ return 0;\r
+ }\r
+\r
+ if(prk29_uart_dma_t->rx_dma_start == 1){\r
+ return 0;\r
+ }\r
+\r
+ if(-1 == serial_rk_init_dma_rx(port)){\r
+ dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");\r
+ return -1;\r
+ }\r
+\r
+ if (rk29_dma_enqueue(prk29_uart_dma_t->rx_dmach, (void *)up, prk29_uart_dma_t->rx_phy_addr,\r
+ prk29_uart_dma_t->rx_buffer_size/2)) {\r
+ dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
+ return -1;\r
+ }\r
+\r
+ if (rk29_dma_enqueue(prk29_uart_dma_t->rx_dmach, (void *)up,\r
+ prk29_uart_dma_t->rx_phy_addr+prk29_uart_dma_t->rx_buffer_size/2,\r
+ prk29_uart_dma_t->rx_buffer_size/2)) {\r
+ dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
+ return -1;\r
+ }\r
+\r
+ rk29_dma_ctrl(prk29_uart_dma_t->rx_dmach, RK29_DMAOP_START);\r
+ prk29_uart_dma_t->rx_dma_start = 1;\r
+ if(prk29_uart_dma_t->use_timer == 1){\r
+ mod_timer(&prk29_uart_dma_t->rx_timer, jiffies +\r
+ msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
+ }\r
+ up->port_activity = jiffies;\r
+ return 1;\r
+}\r
+\r
+static void serial_rk_update_rb_addr(struct uart_rk_port *up){\r
+ dma_addr_t current_pos = 0;\r
+ dma_addr_t rx_current_pos = 0;\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+ spin_lock(&(up->prk29_uart_dma_t->rx_lock));\r
+ rk29_dma_getposition(prk29_uart_dma_t->rx_dmach, ¤t_pos, &rx_current_pos);\r
+\r
+ prk29_uart_dma_t->rb_cur_pos = (rx_current_pos - prk29_uart_dma_t->rx_phy_addr);\r
+ prk29_uart_dma_t->rx_size = CIRC_CNT(prk29_uart_dma_t->rb_cur_pos,\r
+ prk29_uart_dma_t->rb_pre_pos, prk29_uart_dma_t->rx_buffer_size);\r
+\r
+ spin_unlock(&(up->prk29_uart_dma_t->rx_lock));\r
+}\r
+\r
+static void serial_rk_report_dma_rx(unsigned long uart)\r
+{\r
+ struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
+ struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
+ if(prk29_uart_dma_t->use_timer == 1){\r
+ serial_rk_update_rb_addr(up);\r
+ }\r
+ if(prk29_uart_dma_t->rx_size > 0) {\r
+ spin_lock(&(up->prk29_uart_dma_t->rx_lock));\r
+\r
+ if(prk29_uart_dma_t->rb_cur_pos > prk29_uart_dma_t->rb_pre_pos){\r
+ tty_insert_flip_string(up->port.state->port.tty, prk29_uart_dma_t->rx_buffer\r
+ + prk29_uart_dma_t->rb_pre_pos, prk29_uart_dma_t->rx_size);\r
+ tty_flip_buffer_push(up->port.state->port.tty);\r
+ }\r
+ else if(prk29_uart_dma_t->rb_cur_pos < prk29_uart_dma_t->rb_pre_pos){\r
+\r
+ tty_insert_flip_string(up->port.state->port.tty, prk29_uart_dma_t->rx_buffer\r
+ + prk29_uart_dma_t->rb_pre_pos, CIRC_CNT_TO_END(prk29_uart_dma_t->rb_cur_pos,\r
+ prk29_uart_dma_t->rb_pre_pos, prk29_uart_dma_t->rx_buffer_size));\r
+ tty_flip_buffer_push(up->port.state->port.tty);\r
+\r
+ if(prk29_uart_dma_t->rb_cur_pos != 0){\r
+ tty_insert_flip_string(up->port.state->port.tty, prk29_uart_dma_t->rx_buffer,\r
+ prk29_uart_dma_t->rb_cur_pos);\r
+ tty_flip_buffer_push(up->port.state->port.tty);\r
+ }\r
+ }\r
+\r
+ prk29_uart_dma_t->rb_pre_pos = (prk29_uart_dma_t->rb_pre_pos + prk29_uart_dma_t->rx_size)\r
+ & (prk29_uart_dma_t->rx_buffer_size - 1);\r
+ up->port.icount.rx += prk29_uart_dma_t->rx_size;\r
+ spin_unlock(&(up->prk29_uart_dma_t->rx_lock));\r
+ prk29_uart_dma_t->rx_timeout = 7;\r
+ up->port_activity = jiffies;\r
+ }\r
+\r
+\r
+#if 1\r
+ if (jiffies_to_msecs(jiffies - up->port_activity) < RX_TIMEOUT) {\r
+ if(prk29_uart_dma_t->use_timer == 1){\r
+ mod_timer(&prk29_uart_dma_t->rx_timer, jiffies + msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
+ }\r
+ } else {\r
+\r
+#if 1\r
+\r
+\r
+ prk29_uart_dma_t->rx_timeout = 20;\r
+ mod_timer(&prk29_uart_dma_t->rx_timer, jiffies + msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
+#else\r
+// serial_out(up, 0x2a, 0x01);\r
+ serial_rk_release_dma_rx(&up->port);\r
+ serial_out(up, 0x2a, 0x01);\r
+ up->ier |= (UART_IER_RDI | UART_IER_RLSI);\r
+ serial_out(up, UART_IER, up->ier);\r
+// serial_out(up, 0x22, 0x01);\r
+ dev_info(up->port.dev, "*****enable recv int*****\n");\r
+\r
+ //serial_rk_start_rx_dma(&up->port);\r
+#endif\r
+ }\r
+\r
+\r
+#else\r
+ if(prk29_uart_dma_t->use_timer == 1){\r
+ mod_timer(&prk29_uart_dma_t->rx_timer, jiffies + msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
+ }\r
+#endif\r
+\r
+}\r
+\r
+static void serial_rk_rx_timeout(unsigned long uart)\r
+{\r
+ struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
+\r
+ //serial_rk_report_dma_rx(up);\r
+ queue_work(up->uart_wq, &up->uart_work);\r
+}\r
+\r
+static void serial_rk_report_revdata_workfunc(struct work_struct *work)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(work, struct uart_rk_port, uart_work);\r
+ serial_rk_report_dma_rx((unsigned long)up);\r
+ spin_lock(&(up->prk29_uart_dma_t->rx_lock));\r
+\r
+ if(up->prk29_uart_dma_t->use_timer == 1){\r
+\r
+ }else{\r
+ tty_insert_flip_string(up->port.state->port.tty, up->fifo, up->fifo_size);\r
+ tty_flip_buffer_push(up->port.state->port.tty);\r
+ up->port.icount.rx += up->fifo_size;\r
+ }\r
+\r
+ spin_unlock(&(up->prk29_uart_dma_t->rx_lock));\r
+\r
+}\r
+\r
+\r
+static void serial_rk_start_dma_rx(struct work_struct *work)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(work, struct uart_rk_port, uart_work_rx);\r
+ serial_rk_start_rx_dma(&up->port);\r
+}\r
+\r
+\r
+\r
+static void\r
+receive_chars(struct uart_rk_port *up, unsigned int *status)\r
+{\r
+ struct tty_struct *tty = up->port.state->port.tty;\r
+ unsigned char ch, lsr = *status;\r
+ int max_count = 256;\r
+ char flag;\r
+\r
+ do {\r
+ if (likely(lsr & UART_LSR_DR))\r
+ ch = serial_in(up, UART_RX);\r
+ else\r
+ /*\r
+ * Intel 82571 has a Serial Over Lan device that will\r
+ * set UART_LSR_BI without setting UART_LSR_DR when\r
+ * it receives a break. To avoid reading from the\r
+ * receive buffer without UART_LSR_DR bit set, we\r
+ * just force the read character to be 0\r
+ */\r
+ ch = 0;\r
+\r
+ flag = TTY_NORMAL;\r
+ up->port.icount.rx++;\r
+\r
+ lsr |= up->lsr_saved_flags;\r
+ up->lsr_saved_flags = 0;\r
+\r
+ if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {\r
+ /*\r
+ * For statistics only\r
+ */\r
+ if (lsr & UART_LSR_BI) {\r
+ lsr &= ~(UART_LSR_FE | UART_LSR_PE);\r
+ up->port.icount.brk++;\r
+ /*\r
+ * We do the SysRQ and SAK checking\r
+ * here because otherwise the break\r
+ * may get masked by ignore_status_mask\r
+ * or read_status_mask.\r
+ */\r
+ if (uart_handle_break(&up->port))\r
+ goto ignore_char;\r
+ } else if (lsr & UART_LSR_PE)\r
+ up->port.icount.parity++;\r
+ else if (lsr & UART_LSR_FE)\r
+ up->port.icount.frame++;\r
+ if (lsr & UART_LSR_OE)\r
+ up->port.icount.overrun++;\r
+\r
+\r
+ /*\r
+ * Mask off conditions which should be ignored.\r
+ */\r
+ lsr &= up->port.read_status_mask;\r
+\r
+ if (lsr & UART_LSR_BI) {\r
+ DEBUG_INTR("handling break....");\r
+ flag = TTY_BREAK;\r
+ } else if (lsr & UART_LSR_PE)\r
+ flag = TTY_PARITY;\r
+ else if (lsr & UART_LSR_FE)\r
+ flag = TTY_FRAME;\r
+ }\r
+ if (uart_handle_sysrq_char(&up->port, ch))\r
+ goto ignore_char;\r
+\r
+ uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);\r
+\r
+ignore_char:\r
+ lsr = serial_in(up, UART_LSR);\r
+ } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));\r
+ spin_unlock(&up->port.lock);\r
+ tty_flip_buffer_push(tty);\r
+ spin_lock(&up->port.lock);\r
+ *status = lsr;\r
+}\r
+\r
+static void transmit_chars(struct uart_rk_port *up)\r
+{\r
+ struct circ_buf *xmit = &up->port.state->xmit;\r
+ int count;\r
+\r
+ if (up->port.x_char) {\r
+ serial_out(up, UART_TX, up->port.x_char);\r
+ up->port.icount.tx++;\r
+ up->port.x_char = 0;\r
+ return;\r
+ }\r
+ if (uart_tx_stopped(&up->port)) {\r
+ __stop_tx(up);\r
+ return;\r
+ }\r
+ if (uart_circ_empty(xmit)) {\r
+ __stop_tx(up);\r
+ return;\r
+ }\r
+\r
+ count = up->tx_loadsz;\r
+ do {\r
+ serial_out(up, UART_TX, xmit->buf[xmit->tail]);\r
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
+ up->port.icount.tx++;\r
+ if (uart_circ_empty(xmit))\r
+ break;\r
+ } while (--count > 0);\r
+\r
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
+ uart_write_wakeup(&up->port);\r
+\r
+ DEBUG_INTR("THRE...");\r
+\r
+ if (uart_circ_empty(xmit))\r
+ __stop_tx(up);\r
+}\r
+\r
+static unsigned int check_modem_status(struct uart_rk_port *up)\r
+{\r
+ unsigned int status = serial_in(up, UART_MSR);\r
+\r
+#if 0\r
+ status |= up->msr_saved_flags;\r
+ up->msr_saved_flags = 0;\r
+ if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&\r
+ up->port.state != NULL) {\r
+ if (status & UART_MSR_TERI)\r
+ up->port.icount.rng++;\r
+ if (status & UART_MSR_DDSR)\r
+ up->port.icount.dsr++;\r
+ if (status & UART_MSR_DDCD)\r
+ uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);\r
+ if (status & UART_MSR_DCTS)\r
+ uart_handle_cts_change(&up->port, status & UART_MSR_CTS);\r
+\r
+ wake_up_interruptible(&up->port.state->port.delta_msr_wait);\r
+ }\r
+#endif\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/*\r
+ * This handles the interrupt from one port.\r
+ */\r
+static void serial_rk_handle_port(struct uart_rk_port *up)\r
+{\r
+ unsigned int status;\r
+ unsigned long flags;\r
+ spin_lock_irqsave(&up->port.lock, flags);\r
+\r
+ status = serial_in(up, UART_LSR);\r
+\r
+ DEBUG_INTR("status = %x...", status);\r
+\r
+ if(up->prk29_uart_dma_t->use_dma == 1) {\r
+\r
+ if(up->iir & UART_IIR_RLSI){\r
+\r
+ if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
+ up->port_activity = jiffies;\r
+ up->ier &= ~UART_IER_RLSI;\r
+ up->ier &= ~UART_IER_RDI;\r
+ serial_out(up, UART_IER, up->ier);\r
+ //receive_chars(up, &status);\r
+ //mod_timer(&up->prk29_uart_dma_t->rx_timer, jiffies +\r
+ //msecs_to_jiffies(up->prk29_uart_dma_t->rx_timeout));\r
+ if(serial_rk_start_rx_dma(&up->port) == -1){\r
+ receive_chars(up, &status);\r
+ }\r
+ }\r
+ }\r
+\r
+/*\r
+ if (status & UART_LSR_THRE) {\r
+ transmit_chars(up);\r
+ }\r
+*/\r
+\r
+ }else { //dma mode disable\r
+\r
+ if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
+ receive_chars(up, &status);\r
+ }\r
+ check_modem_status(up);\r
+ if (status & UART_LSR_THRE) {\r
+ transmit_chars(up);\r
+ }\r
+ }\r
+\r
+ spin_unlock_irqrestore(&up->port.lock, flags);\r
+}\r
+\r
+/*\r
+ * This is the serial driver's interrupt routine.\r
+ */\r
+\r
+static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)\r
+{\r
+ struct uart_rk_port *up = dev_id;\r
+ int handled = 0;\r
+ unsigned int iir;\r
+\r
+ iir = serial_in(up, UART_IIR);\r
+ DEBUG_INTR("%s(%d) iir = 0x%02x ", __func__, irq, iir);\r
+ up->iir = iir;\r
+\r
+ if (!(iir & UART_IIR_NO_INT)) {\r
+ serial_rk_handle_port(up);\r
+ handled = 1;\r
+ } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {\r
+ /* The DesignWare APB UART has an Busy Detect (0x07)\r
+ * interrupt meaning an LCR write attempt occured while the\r
+ * UART was busy. The interrupt must be cleared by reading\r
+ * the UART status register (USR) and the LCR re-written. */\r
+ serial_in(up, UART_USR);\r
+ serial_out(up, UART_LCR, up->lcr);\r
+\r
+ handled = 1;\r
+ DEBUG_INTR("busy ");\r
+ }\r
+ DEBUG_INTR("end(%d).\n", handled);\r
+\r
+ return IRQ_RETVAL(handled);\r
+}\r
+\r
+static unsigned int serial_rk_tx_empty(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned long flags;\r
+ unsigned int lsr;\r
+\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+ spin_lock_irqsave(&up->port.lock, flags);\r
+ lsr = serial_in(up, UART_LSR);\r
+ up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;\r
+ spin_unlock_irqrestore(&up->port.lock, flags);\r
+\r
+ return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;\r
+}\r
+\r
+static unsigned int serial_rk_get_mctrl(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned int status;\r
+ unsigned int ret;\r
+\r
+ status = check_modem_status(up);\r
+\r
+ ret = 0;\r
+ if (status & UART_MSR_DCD)\r
+ ret |= TIOCM_CAR;\r
+ if (status & UART_MSR_RI)\r
+ ret |= TIOCM_RNG;\r
+ if (status & UART_MSR_DSR)\r
+ ret |= TIOCM_DSR;\r
+ if (status & UART_MSR_CTS)\r
+ ret |= TIOCM_CTS;\r
+ dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);\r
+ return ret;\r
+}\r
+\r
+static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned char mcr = 0;\r
+\r
+ dev_dbg(port->dev, "+%s\n", __func__);\r
+ if (mctrl & TIOCM_RTS)\r
+ mcr |= UART_MCR_RTS;\r
+ if (mctrl & TIOCM_DTR)\r
+ mcr |= UART_MCR_DTR;\r
+ if (mctrl & TIOCM_OUT1)\r
+ mcr |= UART_MCR_OUT1;\r
+ if (mctrl & TIOCM_OUT2)\r
+ mcr |= UART_MCR_OUT2;\r
+ if (mctrl & TIOCM_LOOP)\r
+ mcr |= UART_MCR_LOOP;\r
+\r
+ mcr |= up->mcr;\r
+\r
+ serial_out(up, UART_MCR, mcr);\r
+ dev_dbg(port->dev, "-%s mcr: 0x%02x\n", __func__, mcr);\r
+}\r
+\r
+static void serial_rk_break_ctl(struct uart_port *port, int break_state)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned long flags;\r
+\r
+ dev_dbg(port->dev, "+%s\n", __func__);\r
+ spin_lock_irqsave(&up->port.lock, flags);\r
+ if (break_state == -1)\r
+ up->lcr |= UART_LCR_SBC;\r
+ else\r
+ up->lcr &= ~UART_LCR_SBC;\r
+ serial_lcr_write(up, up->lcr);\r
+ spin_unlock_irqrestore(&up->port.lock, flags);\r
+ dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);\r
+}\r
+\r
+/*\r
+ * Wait for transmitter & holding register to empty\r
+ */\r
+static void wait_for_xmitr(struct uart_rk_port *up, int bits)\r
+{\r
+ unsigned int status, tmout = 10000;\r
+\r
+ /* Wait up to 10ms for the character(s) to be sent. */\r
+ for (;;) {\r
+ status = serial_in(up, UART_LSR);\r
+\r
+ up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;\r
+\r
+ if ((status & bits) == bits)\r
+ break;\r
+ if (--tmout == 0)\r
+ break;\r
+ udelay(1);\r
+ }\r
+}\r
+\r
+#ifdef CONFIG_CONSOLE_POLL\r
+/*\r
+ * Console polling routines for writing and reading from the uart while\r
+ * in an interrupt or debug context.\r
+ */\r
+\r
+static int serial_rk_get_poll_char(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned char lsr = serial_in(up, UART_LSR);\r
+\r
+ while (!(lsr & UART_LSR_DR))\r
+ lsr = serial_in(up, UART_LSR);\r
+\r
+ return serial_in(up, UART_RX);\r
+}\r
+\r
+static void serial_rk_put_poll_char(struct uart_port *port,\r
+ unsigned char c)\r
+{\r
+ unsigned int ier;\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+\r
+ /*\r
+ * First save the IER then disable the interrupts\r
+ */\r
+ ier = serial_in(up, UART_IER);\r
+ serial_out(up, UART_IER, 0);\r
+\r
+ wait_for_xmitr(up, BOTH_EMPTY);\r
+ /*\r
+ * Send the character out.\r
+ * If a LF, also do CR...\r
+ */\r
+ serial_out(up, UART_TX, c);\r
+ if (c == 10) {\r
+ wait_for_xmitr(up, BOTH_EMPTY);\r
+ serial_out(up, UART_TX, 13);\r
+ }\r
+\r
+ /*\r
+ * Finally, wait for transmitter to become empty\r
+ * and restore the IER\r
+ */\r
+ wait_for_xmitr(up, BOTH_EMPTY);\r
+ serial_out(up, UART_IER, ier);\r
+}\r
+\r
+#endif /* CONFIG_CONSOLE_POLL */\r
+\r
+static int serial_rk_startup(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned long flags;\r
+ int retval;\r
+\r
+\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+\r
+ /*\r
+ * Allocate the IRQ\r
+ */\r
+ retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,\r
+ up->name, up);\r
+ if (retval)\r
+ return retval;\r
+\r
+ up->mcr = 0;\r
+\r
+ /*\r
+ * Clear the FIFO buffers and disable them.\r
+ * (they will be reenabled in set_termios())\r
+ */\r
+ serial_rk_clear_fifos(up);\r
+\r
+ /*\r
+ * Clear the interrupt registers.\r
+ */\r
+ (void) serial_in(up, UART_LSR);\r
+ (void) serial_in(up, UART_RX);\r
+ (void) serial_in(up, UART_IIR);\r
+ (void) serial_in(up, UART_MSR);\r
+\r
+ /*\r
+ * Now, initialize the UART\r
+ */\r
+ serial_lcr_write(up, UART_LCR_WLEN8);\r
+\r
+ spin_lock_irqsave(&up->port.lock, flags);\r
+\r
+ /*\r
+ * Most PC uarts need OUT2 raised to enable interrupts.\r
+ */\r
+ up->port.mctrl |= TIOCM_OUT2;\r
+\r
+ serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
+\r
+ spin_unlock_irqrestore(&up->port.lock, flags);\r
+\r
+ /*\r
+ * Clear the interrupt registers again for luck, and clear the\r
+ * saved flags to avoid getting false values from polling\r
+ * routines or the previous session.\r
+ */\r
+ serial_in(up, UART_LSR);\r
+ serial_in(up, UART_RX);\r
+ serial_in(up, UART_IIR);\r
+ serial_in(up, UART_MSR);\r
+ up->lsr_saved_flags = 0;\r
+#if 0\r
+ up->msr_saved_flags = 0;\r
+#endif\r
+\r
+\r
+ if (1 == up->prk29_uart_dma_t->use_dma) {\r
+\r
+ if(up->port.state->xmit.buf != up->prk29_uart_dma_t->tx_buffer){\r
+ free_page((unsigned long)up->port.state->xmit.buf);\r
+ up->port.state->xmit.buf = up->prk29_uart_dma_t->tx_buffer;\r
+ }\r
+\r
+#if 1\r
+ serial_rk_start_rx_dma(&up->port);\r
+#else\r
+ up->ier |= UART_IER_RDI;\r
+ up->ier |= UART_IER_RLSI;\r
+ serial_out(up, UART_IER, up->ier);\r
+#endif\r
+ up->port_activity = jiffies;\r
+\r
+ }else{\r
+ up->ier |= UART_IER_RDI;\r
+ up->ier |= UART_IER_RLSI;\r
+ serial_out(up, UART_IER, up->ier);\r
+ }\r
+\r
+ /*\r
+ * Finally, enable interrupts. Note: Modem status interrupts\r
+ * are set via set_termios(), which will be occurring imminently\r
+ * anyway, so we don't enable them here.\r
+ */\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+static void serial_rk_shutdown(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned long flags;\r
+\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+ /*\r
+ * Disable interrupts from this port\r
+ */\r
+ up->ier = 0;\r
+ serial_out(up, UART_IER, 0);\r
+\r
+ spin_lock_irqsave(&up->port.lock, flags);\r
+ up->port.mctrl &= ~TIOCM_OUT2;\r
+ serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
+ spin_unlock_irqrestore(&up->port.lock, flags);\r
+\r
+ /*\r
+ * Disable break condition and FIFOs\r
+ */\r
+ serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);\r
+ serial_rk_clear_fifos(up);\r
+\r
+ /*\r
+ * Read data port to reset things, and then free the irq\r
+ */\r
+ (void) serial_in(up, UART_RX);\r
+\r
+ free_irq(up->port.irq, up);\r
+}\r
+\r
+static void\r
+serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,\r
+ struct ktermios *old)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+ unsigned char cval, fcr = 0;\r
+ unsigned long flags, bits;\r
+ unsigned int baud, quot;\r
+\r
+ dev_dbg(port->dev, "+%s\n", __func__);\r
+\r
+ //start bit\r
+ bits += 1;\r
+ switch (termios->c_cflag & CSIZE) {\r
+ case CS5:\r
+ cval = UART_LCR_WLEN5;\r
+ bits += 5;\r
+ break;\r
+ case CS6:\r
+ cval = UART_LCR_WLEN6;\r
+ bits += 6;\r
+ break;\r
+ case CS7:\r
+ cval = UART_LCR_WLEN7;\r
+ bits += 7;\r
+ break;\r
+ default:\r
+ case CS8:\r
+ cval = UART_LCR_WLEN8;\r
+ bits += 8;\r
+ break;\r
+ }\r
+\r
+ if (termios->c_cflag & CSTOPB){\r
+ cval |= UART_LCR_STOP;\r
+ bits += 2;\r
+ }\r
+ else{\r
+ bits += 1;\r
+ }\r
+ if (termios->c_cflag & PARENB){\r
+ cval |= UART_LCR_PARITY;\r
+ bits += 1;\r
+ }\r
+ if (!(termios->c_cflag & PARODD)){\r
+ cval |= UART_LCR_EPAR;\r
+ }\r
+#ifdef CMSPAR\r
+ if (termios->c_cflag & CMSPAR)\r
+ cval |= UART_LCR_SPAR;\r
+#endif\r
+\r
+ /*\r
+ * Ask the core to calculate the divisor for us.\r
+ */\r
+ baud = uart_get_baud_rate(port, termios, old,\r
+ port->uartclk / 16 / 0xffff,\r
+ port->uartclk / 16);\r
+\r
+ quot = uart_get_divisor(port, baud);\r
+\r
+\r
+ DEBUG_INTR(up->port.dev, "*****baud:%d*******\n", baud);\r
+ DEBUG_INTR(up->port.dev, "*****quot:%d*******\n", quot);\r
+\r
+ if (baud < 2400){\r
+ fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;\r
+ }\r
+ else{\r
+ //added by hhb@rock-chips.com\r
+ if(up->prk29_uart_dma_t->use_timer == 1){\r
+ fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_01;\r
+ //set time out value according to the baud rate\r
+/*\r
+ up->prk29_uart_dma_t->rx_timeout = bits*1000*1024/baud + 1;\r
+\r
+ if(up->prk29_uart_dma_t->rx_timeout < 10){\r
+ up->prk29_uart_dma_t->rx_timeout = 10;\r
+ }\r
+ if(up->prk29_uart_dma_t->rx_timeout > 25){\r
+ up->prk29_uart_dma_t->rx_timeout = 25;\r
+ }\r
+ printk("%s:time:%d, bits:%d, baud:%d\n", __func__, up->prk29_uart_dma_t->rx_timeout, bits, baud);\r
+ up->prk29_uart_dma_t->rx_timeout = 7;\r
+*/\r
+ }\r
+ else{\r
+ fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | UART_FCR_T_TRIG_01;\r
+ }\r
+ }\r
+\r
+ /*\r
+ * MCR-based auto flow control. When AFE is enabled, RTS will be\r
+ * deasserted when the receive FIFO contains more characters than\r
+ * the trigger, or the MCR RTS bit is cleared. In the case where\r
+ * the remote UART is not using CTS auto flow control, we must\r
+ * have sufficient FIFO entries for the latency of the remote\r
+ * UART to respond. IOW, at least 32 bytes of FIFO.\r
+ */\r
+ up->mcr &= ~UART_MCR_AFE;\r
+ if (termios->c_cflag & CRTSCTS){\r
+ up->mcr |= UART_MCR_AFE;\r
+ //dev_info(up->port.dev, "*****UART_MCR_AFE*******\n");\r
+ }\r
+\r
+\r
+ /*\r
+ * Ok, we're now changing the port state. Do it with\r
+ * interrupts disabled.\r
+ */\r
+ spin_lock_irqsave(&up->port.lock, flags);\r
+\r
+ /*\r
+ * Update the per-port timeout.\r
+ */\r
+ uart_update_timeout(port, termios->c_cflag, baud);\r
+\r
+ up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;\r
+ if (termios->c_iflag & INPCK)\r
+ up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;\r
+ if (termios->c_iflag & (BRKINT | PARMRK))\r
+ up->port.read_status_mask |= UART_LSR_BI;\r
+\r
+ /*\r
+ * Characteres to ignore\r
+ */\r
+ up->port.ignore_status_mask = 0;\r
+ if (termios->c_iflag & IGNPAR)\r
+ up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;\r
+ if (termios->c_iflag & IGNBRK) {\r
+ up->port.ignore_status_mask |= UART_LSR_BI;\r
+ /*\r
+ * If we're ignoring parity and break indicators,\r
+ * ignore overruns too (for real raw support).\r
+ */\r
+ if (termios->c_iflag & IGNPAR)\r
+ up->port.ignore_status_mask |= UART_LSR_OE;\r
+ }\r
+\r
+ /*\r
+ * ignore all characters if CREAD is not set\r
+ */\r
+ if ((termios->c_cflag & CREAD) == 0)\r
+ up->port.ignore_status_mask |= UART_LSR_DR;\r
+\r
+ /*\r
+ * CTS flow control flag and modem status interrupts\r
+ */\r
+ up->ier &= ~UART_IER_MSI;\r
+#if 0\r
+ if (UART_ENABLE_MS(&up->port, termios->c_cflag))\r
+ up->ier |= UART_IER_MSI;\r
+#endif\r
+\r
+ serial_out(up, UART_IER, up->ier);\r
+\r
+ serial_lcr_write(up, cval | UART_LCR_DLAB);/* set DLAB */\r
+\r
+ serial_dl_write(up, quot);\r
+\r
+ serial_lcr_write(up, cval); /* reset DLAB */\r
+ up->lcr = cval; /* Save LCR */\r
+\r
+ serial_out(up, UART_FCR, fcr); /* set fcr */\r
+// fcr |= UART_FCR_DMA_SELECT;\r
+// serial_out(up, UART_FCR, fcr); /* set fcr */\r
+ serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
+\r
+ spin_unlock_irqrestore(&up->port.lock, flags);\r
+ /* Don't rewrite B0 */\r
+ if (tty_termios_baud_rate(termios))\r
+ tty_termios_encode_baud_rate(termios, baud, baud);\r
+ dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);\r
+}\r
+\r
+#if 0\r
+static void\r
+serial_rk_set_ldisc(struct uart_port *port, int new)\r
+{\r
+ if (new == N_PPS) {\r
+ port->flags |= UPF_HARDPPS_CD;\r
+ serial_rk_enable_ms(port);\r
+ } else\r
+ port->flags &= ~UPF_HARDPPS_CD;\r
+}\r
+#endif\r
+\r
+static void\r
+serial_rk_pm(struct uart_port *port, unsigned int state,\r
+ unsigned int oldstate)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+\r
+ dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
+ if (state)\r
+ clk_disable(up->clk);\r
+ else\r
+ clk_enable(up->clk);\r
+}\r
+\r
+static void serial_rk_release_port(struct uart_port *port)\r
+{\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+}\r
+\r
+static int serial_rk_request_port(struct uart_port *port)\r
+{\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+ return 0;\r
+}\r
+\r
+static void serial_rk_config_port(struct uart_port *port, int flags)\r
+{\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+ port->type = PORT_RK;\r
+}\r
+\r
+static int\r
+serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)\r
+{\r
+ /* we don't want the core code to modify any port params */\r
+ dev_dbg(port->dev, "%s\n", __func__);\r
+ return -EINVAL;\r
+}\r
+\r
+static const char *\r
+serial_rk_type(struct uart_port *port)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+\r
+ dev_dbg(port->dev, "%s: %s\n", __func__, up->name);\r
+ return up->name;\r
+}\r
+\r
+static struct uart_ops serial_rk_pops = {\r
+ .tx_empty = serial_rk_tx_empty,\r
+ .set_mctrl = serial_rk_set_mctrl,\r
+ .get_mctrl = serial_rk_get_mctrl,\r
+ .stop_tx = serial_rk_stop_tx,\r
+ .start_tx = serial_rk_start_tx,\r
+ .stop_rx = serial_rk_stop_rx,\r
+ .enable_ms = serial_rk_enable_ms,\r
+ .break_ctl = serial_rk_break_ctl,\r
+ .startup = serial_rk_startup,\r
+ .shutdown = serial_rk_shutdown,\r
+ .set_termios = serial_rk_set_termios,\r
+#if 0\r
+ .set_ldisc = serial_rk_set_ldisc,\r
+#endif\r
+ .pm = serial_rk_pm,\r
+ .type = serial_rk_type,\r
+ .release_port = serial_rk_release_port,\r
+ .request_port = serial_rk_request_port,\r
+ .config_port = serial_rk_config_port,\r
+ .verify_port = serial_rk_verify_port,\r
+#ifdef CONFIG_CONSOLE_POLL\r
+ .poll_get_char = serial_rk_get_poll_char,\r
+ .poll_put_char = serial_rk_put_poll_char,\r
+#endif\r
+};\r
+\r
+#ifdef CONFIG_SERIAL_RK_CONSOLE\r
+\r
+static struct uart_rk_port *serial_rk_console_ports[UART_NR];\r
+\r
+static void serial_rk_console_putchar(struct uart_port *port, int ch)\r
+{\r
+ struct uart_rk_port *up =\r
+ container_of(port, struct uart_rk_port, port);\r
+\r
+ wait_for_xmitr(up, UART_LSR_THRE);\r
+ serial_out(up, UART_TX, ch);\r
+}\r
+\r
+/*\r
+ * Print a string to the serial port trying not to disturb\r
+ * any possible real use of the port...\r
+ *\r
+ * The console_lock must be held when we get here.\r
+ */\r
+static void\r
+serial_rk_console_write(struct console *co, const char *s, unsigned int count)\r
+{\r
+ struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
+ unsigned long flags;\r
+ unsigned int ier;\r
+ int locked = 1;\r
+\r
+ touch_nmi_watchdog();\r
+\r
+ local_irq_save(flags);\r
+ if (up->port.sysrq) {\r
+ /* serial_rk_handle_port() already took the lock */\r
+ locked = 0;\r
+ } else if (oops_in_progress) {\r
+ locked = spin_trylock(&up->port.lock);\r
+ } else\r
+ spin_lock(&up->port.lock);\r
+\r
+ /*\r
+ * First save the IER then disable the interrupts\r
+ */\r
+ ier = serial_in(up, UART_IER);\r
+\r
+ serial_out(up, UART_IER, 0);\r
+\r
+ uart_console_write(&up->port, s, count, serial_rk_console_putchar);\r
+\r
+ /*\r
+ * Finally, wait for transmitter to become empty\r
+ * and restore the IER\r
+ */\r
+ wait_for_xmitr(up, BOTH_EMPTY);\r
+ serial_out(up, UART_IER, ier);\r
+\r
+#if 0\r
+ /*\r
+ * The receive handling will happen properly because the\r
+ * receive ready bit will still be set; it is not cleared\r
+ * on read. However, modem control will not, we must\r
+ * call it if we have saved something in the saved flags\r
+ * while processing with interrupts off.\r
+ */\r
+ if (up->msr_saved_flags)\r
+ check_modem_status(up);\r
+#endif\r
+\r
+ if (locked)\r
+ spin_unlock(&up->port.lock);\r
+ local_irq_restore(flags);\r
+}\r
+\r
+static int __init serial_rk_console_setup(struct console *co, char *options)\r
+{\r
+ struct uart_rk_port *up;\r
+ int baud = 115200;\r
+ int bits = 8;\r
+ int parity = 'n';\r
+ int flow = 'n';\r
+\r
+ if (unlikely(co->index >= UART_NR || co->index < 0))\r
+ return -ENODEV;\r
+\r
+ if (serial_rk_console_ports[co->index] == NULL)\r
+ return -ENODEV;\r
+ up = serial_rk_console_ports[co->index];\r
+\r
+ if (options)\r
+ uart_parse_options(options, &baud, &parity, &bits, &flow);\r
+\r
+ return uart_set_options(&up->port, co, baud, parity, bits, flow);\r
+}\r
+\r
+static struct console serial_rk_console = {\r
+ .name = "ttyS",\r
+ .write = serial_rk_console_write,\r
+ .device = uart_console_device,\r
+ .setup = serial_rk_console_setup,\r
+ .flags = CON_PRINTBUFFER | CON_ANYTIME,\r
+ .index = -1,\r
+ .data = &serial_rk_reg,\r
+};\r
+\r
+static void serial_rk_add_console_port(struct uart_rk_port *up)\r
+{\r
+ serial_rk_console_ports[up->pdev->id] = up;\r
+}\r
+\r
+#define SERIAL_CONSOLE &serial_rk_console\r
+#else\r
+#define SERIAL_CONSOLE NULL\r
+\r
+static inline void serial_rk_add_console_port(struct uart_rk_port *up)\r
+{}\r
+\r
+#endif\r
+\r
+static struct uart_driver serial_rk_reg = {\r
+ .owner = THIS_MODULE,\r
+ .driver_name = "rk29_serial",\r
+ .dev_name = "ttyS",\r
+ .major = TTY_MAJOR,\r
+ .minor = 64,\r
+ .cons = SERIAL_CONSOLE,\r
+ .nr = UART_NR,\r
+};\r
+\r
+static int __devinit serial_rk_probe(struct platform_device *pdev)\r
+{\r
+ struct uart_rk_port *up;\r
+ struct resource *mem;\r
+ int irq;\r
+ int ret = -ENOSPC;\r
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
+ if (!mem) {\r
+ dev_err(&pdev->dev, "no mem resource?\n");\r
+ return -ENODEV;\r
+ }\r
+\r
+ irq = platform_get_irq(pdev, 0);\r
+ if (irq < 0) {\r
+ dev_err(&pdev->dev, "no irq resource?\n");\r
+ return irq;\r
+ }\r
+\r
+ if (!request_mem_region(mem->start, (mem->end - mem->start) + 1,\r
+ pdev->dev.driver->name)) {\r
+ dev_err(&pdev->dev, "memory region already claimed\n");\r
+ return -EBUSY;\r
+ }\r
+\r
+ up = kzalloc(sizeof(*up), GFP_KERNEL);\r
+ if (up == NULL) {\r
+ ret = -ENOMEM;\r
+ goto do_release_region;\r
+ }\r
+\r
+ sprintf(up->name, "rk29_serial.%d", pdev->id);\r
+ up->pdev = pdev;\r
+ up->clk = clk_get(&pdev->dev, "uart");\r
+ if (unlikely(IS_ERR(up->clk))) {\r
+ ret = PTR_ERR(up->clk);\r
+ goto do_free;\r
+ }\r
+ up->tx_loadsz = 30;\r
+ up->prk29_uart_dma_t = &rk29_uart_ports_dma_t[pdev->id];\r
+ up->port.dev = &pdev->dev;\r
+ up->port.type = PORT_RK;\r
+ up->port.irq = irq;\r
+ up->port.iotype = UPIO_DWAPB;\r
+\r
+ up->port.regshift = 2;\r
+ up->port.fifosize = 32;\r
+ up->port.ops = &serial_rk_pops;\r
+ up->port.line = pdev->id;\r
+ up->port.iobase = mem->start;\r
+ up->port.membase = ioremap_nocache(mem->start, mem->end - mem->start + 1);\r
+ if (!up->port.membase) {\r
+ ret = -ENOMEM;\r
+ goto do_put_clk;\r
+ }\r
+ up->port.mapbase = mem->start;\r
+ up->port.irqflags = 0;\r
+ up->port.uartclk = clk_get_rate(up->clk);\r
+\r
+ /* set dma config */\r
+ if(1 == up->prk29_uart_dma_t->use_dma) {\r
+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\r
+\r
+ //timer\r
+ up->prk29_uart_dma_t->use_timer = USE_TIMER;\r
+ up->prk29_uart_dma_t->rx_timer.function = serial_rk_rx_timeout;\r
+ up->prk29_uart_dma_t->rx_timer.data = (unsigned long)up;\r
+ up->prk29_uart_dma_t->rx_timeout = 7;\r
+ up->prk29_uart_dma_t->rx_timer.expires = jiffies + msecs_to_jiffies(up->prk29_uart_dma_t->rx_timeout);\r
+ init_timer(&up->prk29_uart_dma_t->rx_timer);\r
+ //tx buffer\r
+ up->prk29_uart_dma_t->tx_buffer_size = UART_XMIT_SIZE;\r
+ up->prk29_uart_dma_t->tx_buffer = dmam_alloc_coherent(up->port.dev, up->prk29_uart_dma_t->tx_buffer_size,\r
+ &up->prk29_uart_dma_t->tx_phy_addr, DMA_MEMORY_MAP);\r
+ if(!up->prk29_uart_dma_t->tx_buffer){\r
+ dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");\r
+ }\r
+ else{\r
+ dev_info(up->port.dev, "dma_tx_buffer 0x%08x\n", (unsigned) up->prk29_uart_dma_t->tx_buffer);\r
+ dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->prk29_uart_dma_t->tx_phy_addr);\r
+ }\r
+ //rx buffer\r
+ up->prk29_uart_dma_t->rx_buffer_size = UART_XMIT_SIZE*32;\r
+ up->prk29_uart_dma_t->rx_buffer = dmam_alloc_coherent(up->port.dev, up->prk29_uart_dma_t->rx_buffer_size,\r
+ &up->prk29_uart_dma_t->rx_phy_addr, DMA_MEMORY_MAP);\r
+ up->prk29_uart_dma_t->rb_pre_pos = 0;\r
+ if(!up->prk29_uart_dma_t->rx_buffer){\r
+ dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");\r
+ }\r
+ else {\r
+ dev_info(up->port.dev, "dma_rx_buffer 0x%08x\n", (unsigned) up->prk29_uart_dma_t->rx_buffer);\r
+ dev_info(up->port.dev, "up 0x%08x\n", (unsigned)up->prk29_uart_dma_t);\r
+ }\r
+\r
+ // work queue\r
+ INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);\r
+ INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);\r
+ up->uart_wq = create_singlethread_workqueue("uart_workqueue");\r
+ up->prk29_uart_dma_t->rx_dma_start = 0;\r
+ spin_lock_init(&(up->prk29_uart_dma_t->tx_lock));\r
+ spin_lock_init(&(up->prk29_uart_dma_t->rx_lock));\r
+ serial_rk_init_dma_rx(&up->port);\r
+ serial_rk_init_dma_tx(&up->port);\r
+ up->ier |= THRE_MODE; // enable THRE interrupt mode\r
+ serial_out(up, UART_IER, up->ier);\r
+ clk_enable(up->clk); // enable the config uart clock\r
+ }\r
+\r
+\r
+ serial_rk_add_console_port(up);\r
+ ret = uart_add_one_port(&serial_rk_reg, &up->port);\r
+ if (ret != 0)\r
+ goto do_iounmap;\r
+\r
+ platform_set_drvdata(pdev, up);\r
+ dev_info(&pdev->dev, "membase 0x%08x\n", (unsigned) up->port.membase);\r
+\r
+ return 0;\r
+\r
+do_iounmap:\r
+ iounmap(up->port.membase);\r
+ up->port.membase = NULL;\r
+do_put_clk:\r
+ clk_put(up->clk);\r
+do_free:\r
+ kfree(up);\r
+do_release_region:\r
+ release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
+ return ret;\r
+}\r
+\r
+static int __devexit serial_rk_remove(struct platform_device *pdev)\r
+{\r
+ struct uart_rk_port *up = platform_get_drvdata(pdev);\r
+\r
+ platform_set_drvdata(pdev, NULL);\r
+ if (up) {\r
+ struct resource *mem;\r
+ destroy_workqueue(up->uart_wq);\r
+ uart_remove_one_port(&serial_rk_reg, &up->port);\r
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
+ iounmap(up->port.membase);\r
+ up->port.membase = NULL;\r
+ clk_put(up->clk);\r
+ kfree(up);\r
+ release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)\r
+{\r
+ struct uart_rk_port *up = platform_get_drvdata(dev);\r
+\r
+ if (up)\r
+ uart_suspend_port(&serial_rk_reg, &up->port);\r
+ printk("%s:%s\n", __func__, dev->name);\r
+ return 0;\r
+}\r
+\r
+static int serial_rk_resume(struct platform_device *dev)\r
+{\r
+ struct uart_rk_port *up = platform_get_drvdata(dev);\r
+\r
+ if (up)\r
+ uart_resume_port(&serial_rk_reg, &up->port);\r
+ printk("%s:%s\n", __func__, dev->name);\r
+ return 0;\r
+}\r
+\r
+static struct platform_driver serial_rk_driver = {\r
+ .probe = serial_rk_probe,\r
+ .remove = __devexit_p(serial_rk_remove),\r
+ .suspend = serial_rk_suspend,\r
+ .resume = serial_rk_resume,\r
+ .driver = {\r
+#if defined(CONFIG_SERIAL_RK29_STANDAR)\r
+ .name = "rk29_serial",\r
+#elif defined(CONFIG_SERIAL_RK2818)\r
+ .name = "rk2818_serial",\r
+#else\r
+ .name = "rk_serial",\r
+#endif\r
+ .owner = THIS_MODULE,\r
+ },\r
+};\r
+\r
+static int __init serial_rk_init(void)\r
+{\r
+ int ret;\r
+\r
+ ret = uart_register_driver(&serial_rk_reg);\r
+ if (ret)\r
+ return ret;\r
+\r
+ ret = platform_driver_register(&serial_rk_driver);\r
+ if (ret != 0)\r
+ uart_unregister_driver(&serial_rk_reg);\r
+\r
+ return ret;\r
+}\r
+\r
+static void __exit serial_rk_exit(void)\r
+{\r
+ platform_driver_unregister(&serial_rk_driver);\r
+ uart_unregister_driver(&serial_rk_reg);\r
+}\r
+\r
+module_init(serial_rk_init);\r
+module_exit(serial_rk_exit);\r
+\r
+MODULE_LICENSE("GPL");\r
+MODULE_DESCRIPTION("RK UART driver");\r
+\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff