Fix a bug where we would incorrectly do a sign ext instead of a zero ext
authorChris Lattner <sabre@nondot.org>
Thu, 10 Mar 2005 20:55:51 +0000 (20:55 +0000)
committerChris Lattner <sabre@nondot.org>
Thu, 10 Mar 2005 20:55:51 +0000 (20:55 +0000)
because we were checking the wrong thing.  Thanks to andrew for pointing
this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20554 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

index fb52d11bd3d5edab805da23b9ad579c3b769f529..d4804d98227285d4a38939f4920ea361d2241e04 100644 (file)
@@ -961,7 +961,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
     // Extending a constant?  Just return the constant.
     if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
       SDOperand Tmp = getNode(ISD::TRUNCATE, EVT, N1);
-      if (N1.getOpcode() == ISD::ZERO_EXTEND_INREG)
+      if (Opcode == ISD::ZERO_EXTEND_INREG)
         return getNode(ISD::ZERO_EXTEND, VT, Tmp);
       else
         return getNode(ISD::SIGN_EXTEND, VT, Tmp);