Disbale the broken fold of shift + sz[ext] for now

Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21291 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0a4b88ba6d4170e5287f01dfaa6d1742d7de911c..1926c2adb5b4482e6110dbdb2bf93bcbdcf24089 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -773,7 +773,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     case ISD::AND:
       if (!C2) return N2;         // X and 0 -> 0
       if (N2C->isAllOnesValue())
-       return N1;                // X and -1 -> X
+        return N1;                // X and -1 -> X
 
       // FIXME: Should add a corresponding version of this for
       // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
@@ -795,13 +795,13 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
 
       // If we are anding the result of a setcc, and we know setcc always
       // returns 0 or 1, simplify the RHS to either be 0 or 1
-      if (N1.getOpcode() == ISD::SETCC && C2 != 1 &&
+      if (N1.getOpcode() == ISD::SETCC &&
           TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
         if (C2 & 1)
-          return getNode(ISD::AND, VT, N1, getConstant(1, VT));
+          return N1;
         else
           return getConstant(0, VT);
-
+      
       if (N1.getOpcode() == ISD::ZEXTLOAD) {
         // If we are anding the result of a zext load, realize that the top bits
         // of the loaded value are already zero to simplify C2.
@@ -941,6 +941,10 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     if (N2.getOpcode() == ISD::FNEG)          // (A- (-B) -> A+B
       return getNode(ISD::ADD, VT, N1, N2.getOperand(0));
     break;
+  // FIXME: figure out how to safely handle things like
+  // int foo(int x) { return 1 << (x & 255); }
+  // int bar() { return foo(256); }
+#if 0
   case ISD::SHL:
   case ISD::SRL:
   case ISD::SRA:
@@ -955,8 +959,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
         if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
           return getNode(Opcode, VT, N1, N2.getOperand(0));
       }
-             
     break;
+#endif
   }
 
   SDNode *&N = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))];
@@ -1039,6 +1043,22 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
               N2.getOperand(0) == N3)
             return getNode(ISD::FABS, VT, N3);
         }
+      // select (setlt X, 0), A, 0 -> and (sra X, size(X)-1, A)
+      if (ConstantSDNode *CN =
+          dyn_cast<ConstantSDNode>(SetCC->getOperand(1)))
+        if (CN->getValue() == 0 && N3C && N3C->getValue() == 0)
+          if (SetCC->getCondition() == ISD::SETLT) {
+            MVT::ValueType XType = SetCC->getOperand(0).getValueType();
+            MVT::ValueType AType = N2.getValueType();
+            if (XType >= AType) {
+              SDOperand Shift = getNode(ISD::SRA, XType, SetCC->getOperand(0),
+                getConstant(MVT::getSizeInBits(XType)-1,
+                            TLI.getShiftAmountTy()));
+              if (XType > AType)
+                Shift = getNode(ISD::TRUNCATE, AType, Shift);
+              return getNode(ISD::AND, AType, Shift, N2);
+            }
+          }
     }
     break;
   case ISD::BRCOND:
@@ -1048,6 +1068,10 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
       else
         return N1;         // Never-taken branch
     break;
+  // FIXME: figure out how to safely handle things like
+  // int foo(int x) { return 1 << (x & 255); }
+  // int bar() { return foo(256); }
+#if 0
   case ISD::SRA_PARTS:
   case ISD::SRL_PARTS:
   case ISD::SHL_PARTS:
@@ -1062,9 +1086,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
         if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
           return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
       }
-
-
     break;
+#endif
   }
 
   SDNode *N = new SDNode(Opcode, N1, N2, N3);

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index f2f3f63e4e561ae4ff043a04ac8c1e0f14f6182a..8090799856395db02a92553a95033b90a162e7bb 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -2126,25 +2126,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     return 0;
     
   case ISD::SELECT: {
-    // We can codegen select (a < 0) ? b : 0 very efficiently compared to a 
-    // conditional branch.  Check for that here.
-    if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val)) {
-      if (ConstantSDNode *CN = 
-          dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
-        if (ConstantSDNode *CNF = 
-            dyn_cast<ConstantSDNode>(N.getOperand(2).Val)) {
-          if (CN->getValue() == 0 && CNF->getValue() == 0 &&
-              SetCC->getCondition() == ISD::SETLT) {
-            Tmp1 = SelectExpr(N.getOperand(1)); // TRUE value
-            Tmp2 = SelectExpr(SetCC->getOperand(0));
-            Tmp3 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::SRAWI, 2, Tmp3).addReg(Tmp2).addImm(31);
-            BuildMI(BB, PPC::AND, 2, Result).addReg(Tmp1).addReg(Tmp3);
-            return Result;
-          }
-        }
-      }
-    }
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
     unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
     Opc = SelectSetCR0(N.getOperand(0));