Back out previous check-in. Incorrect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36503 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 56a2d9452d423af55389aa2e4a5ff1b66a247d4d..48196369addd7b159bd3b25b33797b08ef35ab58 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -56,10 +56,6 @@ class TIt<dag ops, string asm, list<dag> pattern>
 class TIx2<dag ops, string asm, list<dag> pattern>
   : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
 
-// tLEApcrel and tLEApcrelJT
-class TIsx2<dag ops, string asm, list<dag> pattern>
-  : ThumbI<ops, AddrModeTs, Size4Bytes, asm, "", pattern>;
-
 // BR_JT instructions
 class TJTI<dag ops, string asm, list<dag> pattern>
   : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
@@ -513,14 +509,14 @@ let usesCustomDAGSchedInserter = 1 in  // Expanded by the scheduler.
 
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-def tLEApcrel : TIsx2<(ops GPR:$dst, i32imm:$label),
+def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
                     !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
                                           "${:private}PCRELL${:uid}+6))\n"),
                                !strconcat("\tmov $dst, #PCRELV${:uid}\n",
                                   "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
                     []>;
 
-def tLEApcrelJT : TIsx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
+def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
           !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
                                          "${:private}PCRELL${:uid}+4))\n"),
                      !strconcat("\tmov $dst, #PCRELV${:uid}\n",