return N1.getOperand(0);
if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand();
+ return SDOperand(N, 0);
// fold (a+b) -> (a|b) iff a and b share no bits.
if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
// fold (and (sra)) -> (and (srl)) when possible.
if (!MVT::isVector(VT) &&
SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand();
+ return SDOperand(N, 0);
// fold (zext_inreg (extload x)) -> (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) {
MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
// Simplify the expression using non-local knowledge.
if (!MVT::isVector(VT) &&
SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand();
+ return SDOperand(N, 0);
return SDOperand();
}
if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return DAG.getConstant(0, VT);
if (SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand();
+ return SDOperand(N, 0);
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SHL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {