ARM: dts: Put Cygnus core components under core bus

Put all Cygnus core components into "core" node of type "simple-bus" in
bcm-cygnus.dtsi

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 30903ba8f9f6a8289ada3b00e82364cdbfffdab8..97fd305bc8e8af18681f5a80754b6a3712064897 100644 (file)
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -58,6 +58,36 @@
 
        /include/ "bcm-cygnus-clock.dtsi"
 
+       core {
+               compatible = "simple-bus";
+               ranges = <0x00000000 0x19000000 0x1000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               timer@20200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0x20200 0x100>;
+                       interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&periph_clk>;
+               };
+
+               gic: interrupt-controller@21000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       reg = <0x21000 0x1000>,
+                             <0x20100 0x100>;
+               };
+
+               L2: l2-cache {
+                       compatible = "arm,pl310-cache";
+                       reg = <0x22000 0x1000>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+       };
+
        pinctrl: pinctrl@0x0301d0c8 {
                compatible = "brcm,cygnus-pinmux";
                reg = <0x0301d0c8 0x30>,
@@ -227,28 +257,4 @@
 
                brcm,nand-has-wp;
        };
-
-       gic: interrupt-controller@19021000 {
-               compatible = "arm,cortex-a9-gic";
-               #interrupt-cells = <3>;
-               #address-cells = <0>;
-               interrupt-controller;
-               reg = <0x19021000 0x1000>,
-                     <0x19020100 0x100>;
-       };
-
-       L2: l2-cache {
-               compatible = "arm,pl310-cache";
-               reg = <0x19022000 0x1000>;
-               cache-unified;
-               cache-level = <2>;
-       };
-
-       timer@19020200 {
-               compatible = "arm,cortex-a9-global-timer";
-               reg = <0x19020200 0x100>;
-               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&periph_clk>;
-       };
-
 };