delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instruction...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index ae28082decaca860c20837ada9e2d7e31fc9d456..22b1da792b6f7376273b0cab33af018de510aec4 100644 (file)
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -148,3 +148,6 @@
 
 # CHECK:       ldmia   r5!, {r0, r1, r2, r3, r4}
 0x1f 0xcd
+
+# CHECK:       addw    r0, pc, #1050
+0x0f 0xf2 0x1a 0x40

diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp
index 914ea0ee94095fe47d18e6e81d1fe59b2aad458c..e48ac1e67882b930fc363bc93da7c422e4030b96 100644 (file)
--- a/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1632,6 +1632,11 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
     if (Name == "tADR")
       return false;
 
+    // Delegate t2ADR disassembly to the more generic t2ADDri12/t2SUBri12
+    // instructions.
+    if (Name == "t2ADR")
+      return false;
+
     // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr.
     // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s].
     // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s].