x86, AMD: Enable WC+ memory type on family 10 processors

In some cases BIOS may not enable WC+ memory type on family 10
processors, instead converting what would be WC+ memory to CD type.
On guests using nested pages this could result in performance
degradation. This patch enables WC+.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
Link: http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-ostr@amd64.org
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 433a59fb1a7411b97cd0db54d30a3bc727a4aeea..158cde98bbc3a3de06a5cfa10766bf0d1ccae1f5 100644 (file)
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -173,6 +173,7 @@
 #define MSR_AMD64_OSVW_ID_LENGTH       0xc0010140
 #define MSR_AMD64_OSVW_STATUS          0xc0010141
 #define MSR_AMD64_DC_CFG               0xc0011022
+#define MSR_AMD64_BU_CFG2              0xc001102a
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
 #define MSR_AMD64_IBSFETCHPHYSAD       0xc0011032

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index dd4a5b685a00914c59dc296cecf12a3615c95245..721ef3208eb56e1f1e2b8598dc05830d5b17111b 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
        if (c->x86 > 0x11)
                set_cpu_cap(c, X86_FEATURE_ARAT);
 
-       /*
-        * Disable GART TLB Walk Errors on Fam10h. We do this here
-        * because this is always needed when GART is enabled, even in a
-        * kernel which has no MCE support built in.
-        */
        if (c->x86 == 0x10) {
                /*
+                * Disable GART TLB Walk Errors on Fam10h. We do this here
+                * because this is always needed when GART is enabled, even in a
+                * kernel which has no MCE support built in.
                 * BIOS should disable GartTlbWlk Errors themself. If
                 * it doesn't do it here as suggested by the BKDG.
                 *
@@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                        mask |= (1 << 10);
                        wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
                }
+
+               /*
+                * On family 10h BIOS may not have properly enabled WC+ support,
+                * causing it to be converted to CD memtype. This may result in
+                * performance degradation for certain nested-paging guests.
+                * Prevent this conversion by clearing bit 24 in
+                * MSR_AMD64_BU_CFG2.
+                */
+               if (c->x86 == 0x10) {
+                       rdmsrl(MSR_AMD64_BU_CFG2, value);
+                       value &= ~(1ULL << 24);
+                       wrmsrl(MSR_AMD64_BU_CFG2, value);
+               }
        }
 
        rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);