[SEH] Fix llvm.eh.exceptioncode fast register allocation assertion

I called the wrong MachineBasicBlock::addLiveIn() overload.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249786 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index cae343debb63197b94201fc960b1aabad4da804c..a011e4c338c4a15dcfc8f5b5b2da4042992ed8b8 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -264,7 +264,6 @@ private:
   /// personality specific tasks. Returns true if the block should be
   /// instruction selected, false if no code should be emitted for it.
   bool PrepareEHLandingPad();
-  bool PrepareEHPad();
 
   /// \brief Perform instruction selection on all basic blocks in the function.
   void SelectAllBasicBlocks(const Function &Fn);

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index bd60bba318cbebcbe0a261fe6b8aa5b9cfa59f5b..0df05683b4f16d2ec0f5a13cd782a3043a154957 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -950,7 +950,7 @@ bool SelectionDAGISel::PrepareEHLandingPad() {
       // the live in physreg and copy into the vreg.
       MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister();
       assert(EHPhysReg && "target lacks exception pointer register");
-      FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(EHPhysReg, PtrRC);
+      MBB->addLiveIn(EHPhysReg);
       unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
       BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
               TII->get(TargetOpcode::COPY), VReg)

diff --git a/test/CodeGen/X86/seh-exception-code.ll b/test/CodeGen/X86/seh-exception-code.ll
index 28e93617bbad7e83cf18ca41811d50b3c90a5a35..52246907874230953f342a4622ddd51f7269e92a 100644 (file)
--- a/test/CodeGen/X86/seh-exception-code.ll
+++ b/test/CodeGen/X86/seh-exception-code.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s | FileCheck %s
+; RUN: llc -O0 < %s | FileCheck %s
 
 target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-pc-windows-msvc"
@@ -34,8 +35,7 @@ catchendblock:                                    ; preds = %catch.dispatch
 ; CHECK-LABEL: ehcode:
 ; CHECK: xorl %ecx, %ecx
 ; CHECK: callq f
-; CHECK: retq
 
 ; CHECK: # %__except
-; CHECK-NEXT: movl %eax, %ecx
+; CHECK: movl %eax, %ecx
 ; CHECK-NEXT: callq f