staging: silicom: Fix line over 80 characters.

Fix checkpatch.pl issues with line over 80 characters in bp_mod.h

Signed-off-by: Gulsah Kose <gulsah.1004@gmail.com>
Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>

diff --git a/drivers/staging/silicom/bp_mod.h b/drivers/staging/silicom/bp_mod.h
index 9999e6eb03a475a94b9701450a9dab0e3dd2c93c..82b4963e97b63a8e7c87f9adeb0e6711860ac658 100644 (file)
--- a/drivers/staging/silicom/bp_mod.h
+++ b/drivers/staging/silicom/bp_mod.h
@@ -497,11 +497,19 @@ static inline unsigned int jiffies_to_msecs(const unsigned long j)
 #define BPCTLI_STATUS   0x00008        /* Device Status - RO */
 
 /* HW related */
-#define BPCTLI_CTRL_EXT_SDP6_DATA 0x00000040   /* Value of SW Defineable Pin 6 */
-#define BPCTLI_CTRL_EXT_SDP7_DATA 0x00000080   /* Value of SW Defineable Pin 7 */
+#define BPCTLI_CTRL_EXT_SDP6_DATA 0x00000040   /* Value of SW
+                                                                                    * Defineable Pin 6
+                                                                                    */
+#define BPCTLI_CTRL_EXT_SDP7_DATA 0x00000080   /* Value of SW
+                                                                                    * Defineable Pin 7
+                                                                                    */
 #define BPCTLI_CTRL_SDP0_DATA     0x00040000   /* SWDPIN 0 value */
-#define BPCTLI_CTRL_EXT_SDP6_DIR  0x00000400   /* Direction of SDP6 0=in 1=out */
-#define BPCTLI_CTRL_EXT_SDP7_DIR  0x00000800   /* Direction of SDP7 0=in 1=out */
+#define BPCTLI_CTRL_EXT_SDP6_DIR  0x00000400   /* Direction of SDP6
+                                                                                  * 0=in 1=out
+                                                                                  */
+#define BPCTLI_CTRL_EXT_SDP7_DIR  0x00000800   /* Direction of SDP7
+                                                                                  * 0=in 1=out
+                                                                                  */
 #define BPCTLI_CTRL_SDP0_DIR      0x00400000   /* SDP0 Input or output */
 #define BPCTLI_CTRL_SWDPIN1       0x00080000
 #define BPCTLI_CTRL_SDP1_DIR      0x00800000
@@ -565,7 +573,9 @@ static inline unsigned int jiffies_to_msecs(const unsigned long j)
 #define BPCTLI_SWFW_PHY0_SM  0x02
 #define BPCTLI_SWFW_PHY1_SM  0x04
 
-#define BPCTLI_SW_FW_SYNC  0x05B5C     /* Software-Firmware Synchronization - RW */
+#define BPCTLI_SW_FW_SYNC  0x05B5C     /* Software-Firmware
+                                                                    * Synchronization - RW
+                                                                    */
 
 #define BPCTLI_SWSM      0x05B50       /* SW Semaphore */
 #define BPCTLI_FWSM      0x05B54       /* FW Semaphore */
@@ -623,7 +633,8 @@ static inline unsigned int jiffies_to_msecs(const unsigned long j)
 /*#define BP10G_MCLK_DATA_OUT9       BP10G_I2C_CLK_OUT
 #define BP10G_MDIO_DATA_OUT9       BP10G_I2C_DATA_OUT*/
 
-                                      /*#define BP10G_MCLK_DATA_OUT9*//*BP10G_I2C_DATA_OUT */
+                                      /*#define BP10G_MCLK_DATA_OUT9*/
+                                       /*BP10G_I2C_DATA_OUT */
 #define BP10G_MDIO_DATA_OUT9           BP10G_I2C_DATA_OUT      /*BP10G_I2C_CLK_OUT */
 
 /* VIA EOSDP ! */