[SystemZ] Add RISBLG and RISBHG instruction definitions

The next patch will make use of RISBLG for codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187490 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 5906ae5d9c90c9a7298f066dd43af8b78f91844f..6386d16b3d433dfe74c025ebdd50f7e9113d484e 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -867,6 +867,13 @@ let Defs = [CC] in {
   def RISBG : RotateSelectRIEf<"risbg",  0xEC55, GR64, GR64>;
 }
 
+// Forms of RISBG that only affect one word of the destination register.
+// They do not set CC.
+def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
+             Requires<[FeatureHighWord]>;
+def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
+             Requires<[FeatureHighWord]>;
+
 // Rotate second operand left and perform a logical operation with selected
 // bits of the first operand.
 let Defs = [CC] in {

diff --git a/lib/Target/SystemZ/SystemZProcessors.td b/lib/Target/SystemZ/SystemZProcessors.td
index 96fa6a42d042d2284c6ca3117355566f3669c235..7e14aa75862fbdf3b7ec59adc0ba5de0414a86e5 100644 (file)
--- a/lib/Target/SystemZ/SystemZProcessors.td
+++ b/lib/Target/SystemZ/SystemZProcessors.td
@@ -26,8 +26,13 @@ def FeatureLoadStoreOnCond : SystemZFeature<
   "Assume that the load/store-on-condition facility is installed"
 >;
 
+def FeatureHighWord : SystemZFeature<
+  "high-word", "HighWord",
+  "Assume that the high-word facility is installed"
+>;
+
 def : Processor<"z10",   NoItineraries, []>;
 def : Processor<"z196",  NoItineraries,
-                [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
+                [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;
 def : Processor<"zEC12", NoItineraries,
-                [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
+                [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;

diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp
index 43ac1ea4a69b06b43a2135c11c6ab680ce322d91..036ec05d93a83f22662d7b9f4af61f49e8cbb021 100644 (file)
--- a/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -21,7 +21,7 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
                                    const std::string &CPU,
                                    const std::string &FS)
   : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
-    HasLoadStoreOnCond(false), TargetTriple(TT) {
+    HasLoadStoreOnCond(false), HasHighWord(false), TargetTriple(TT) {
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = "z10";

diff --git a/lib/Target/SystemZ/SystemZSubtarget.h b/lib/Target/SystemZ/SystemZSubtarget.h
index 9d5dfc8a1dec5c7340c26e502187f58a14e343dd..4efb58d097b156ddaeaedcd2336a0422dde271f0 100644 (file)
--- a/lib/Target/SystemZ/SystemZSubtarget.h
+++ b/lib/Target/SystemZ/SystemZSubtarget.h
@@ -29,6 +29,7 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
 protected:
   bool HasDistinctOps;
   bool HasLoadStoreOnCond;
+  bool HasHighWord;
 
 private:
   Triple TargetTriple;
@@ -46,6 +47,9 @@ public:
   // Return true if the target has the load/store-on-condition facility.
   bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
 
+  // Return true if the target has the high-word facility.
+  bool hasHighWord() const { return HasHighWord; }
+
   // Return true if GV can be accessed using LARL for reloc model RM
   // and code model CM.
   bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,

diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt
index cf26b653b2a249d752ad928363d62c3862d9e8b3..fa30bd31a0ec3921f1f05a9562bf46d6ef49f4a6 100644 (file)
--- a/test/MC/Disassembler/SystemZ/insns.txt
+++ b/test/MC/Disassembler/SystemZ/insns.txt
@@ -4957,6 +4957,48 @@
 # CHECK: risbg %r4, %r5, 6, 7, 8
 0xec 0x45 0x06 0x07 0x08 0x55
 
+# CHECK: risbhg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x5d
+
+# CHECK: risblg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x51
+
+# CHECK: risblg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x51
+
 # CHECK: rnsbg %r0, %r0, 0, 0, 0
 0xec 0x00 0x00 0x00 0x00 0x54
 

diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s
index a5e21894a3d758775d81e74586a630c62354dacd..ec90c89b4c20c87160411eb7d64577ca801557d7 100644 (file)
--- a/test/MC/SystemZ/insn-bad-z196.s
+++ b/test/MC/SystemZ/insn-bad-z196.s
@@ -74,6 +74,46 @@
        locr    %r0,%r0,-1
        locr    %r0,%r0,16
 
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,256,0,0
+
+       risbhg  %r0,%r0,0,0,-1
+       risbhg  %r0,%r0,0,0,64
+       risbhg  %r0,%r0,0,-1,0
+       risbhg  %r0,%r0,0,256,0
+       risbhg  %r0,%r0,-1,0,0
+       risbhg  %r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,256,0,0
+
+       risblg  %r0,%r0,0,0,-1
+       risblg  %r0,%r0,0,0,64
+       risblg  %r0,%r0,0,-1,0
+       risblg  %r0,%r0,0,256,0
+       risblg  %r0,%r0,-1,0,0
+       risblg  %r0,%r0,256,0,0
+
 #CHECK: error: invalid operand
 #CHECK: sllk   %r0,%r0,-524289
 #CHECK: error: invalid operand

diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s
index f8900566778b07fc4cf3ef0428d23ada36f70f31..eab11d1dd24acef58a86516372e0e48cbbe755df 100644 (file)
--- a/test/MC/SystemZ/insn-bad.s
+++ b/test/MC/SystemZ/insn-bad.s
@@ -2176,6 +2176,16 @@
        risbg   %r0,%r0,-1,0,0
        risbg   %r0,%r0,256,0,0
 
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risbhg %r1, %r2, 0, 0, 0
+
+       risbhg  %r1, %r2, 0, 0, 0
+
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risblg %r1, %r2, 0, 0, 0
+
+       risblg  %r1, %r2, 0, 0, 0
+
 #CHECK: error: invalid operand
 #CHECK: rnsbg  %r0,%r0,0,0,-1
 #CHECK: error: invalid operand

diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s
index f5213b910b9317d1a02be5286b11454eeb4534c6..5f7c27785d78c44a2de0f297bc7a48f132da9385 100644 (file)
--- a/test/MC/SystemZ/insn-good-z196.s
+++ b/test/MC/SystemZ/insn-good-z196.s
@@ -337,6 +337,38 @@
        ork     %r15,%r0,%r0
        ork     %r7,%r8,%r9
 
+#CHECK: risbhg %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d]
+#CHECK: risbhg %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d]
+#CHECK: risbhg %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x5d]
+#CHECK: risbhg %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x5d]
+
+       risbhg  %r0,%r0,0,0,0
+       risbhg  %r0,%r0,0,0,63
+       risbhg  %r0,%r0,0,255,0
+       risbhg  %r0,%r0,255,0,0
+       risbhg  %r0,%r15,0,0,0
+       risbhg  %r15,%r0,0,0,0
+       risbhg  %r4,%r5,6,7,8
+
+#CHECK: risblg %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x51]
+#CHECK: risblg %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x51]
+#CHECK: risblg %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x51]
+#CHECK: risblg %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x51]
+#CHECK: risblg %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x51]
+#CHECK: risblg %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x51]
+#CHECK: risblg %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x51]
+
+       risblg  %r0,%r0,0,0,0
+       risblg  %r0,%r0,0,0,63
+       risblg  %r0,%r0,0,255,0
+       risblg  %r0,%r0,255,0,0
+       risblg  %r0,%r15,0,0,0
+       risblg  %r15,%r0,0,0,0
+       risblg  %r4,%r5,6,7,8
+
 #CHECK: sgrk   %r0, %r0, %r0           # encoding: [0xb9,0xe9,0x00,0x00]
 #CHECK: sgrk   %r0, %r0, %r15          # encoding: [0xb9,0xe9,0xf0,0x00]
 #CHECK: sgrk   %r0, %r15, %r0          # encoding: [0xb9,0xe9,0x00,0x0f]