clk: rockchip: rk3399: fix clk_cifout setting clk error
authorElaine Zhang <zhangqing@rock-chips.com>
Fri, 15 Apr 2016 01:13:32 +0000 (09:13 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Fri, 15 Apr 2016 08:49:42 +0000 (16:49 +0800)
Fix a typo making the clk_cifout access a
wrong clk tree to handle its mux and div.

Change-Id: Ief20e684eadd10b75cf36120df16f13c7581d303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c

index f837528d16f67ab35e449eac1af103d1a7c982b2..bb3a04d234300ec89ceb443a8562348259f6f64b 100644 (file)
@@ -150,7 +150,7 @@ PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)  = { "dummy_vpll", "cpll", "gpll", "xi
 PNAME(mux_dclk_vop0_p)                         = { "dclk_vop0_div", "dummy_dclk_vop0_frac" };
 PNAME(mux_dclk_vop1_p)                         = { "dclk_vop1_div", "dummy_dclk_vop1_frac" };
 
-PNAME(mux_clk_cif_p)                           = { "clk_cifout_div", "xin24m" };
+PNAME(mux_clk_cif_p)                           = { "clk_cifout_src", "xin24m" };
 
 PNAME(mux_pll_src_24m_usbphy480m_p)            = { "xin24m", "clk_usbphy_480m" };
 PNAME(mux_pll_src_24m_pciephy_p)               = { "xin24m", "clk_pciephy_ref100m" };
@@ -1234,11 +1234,12 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(27), 6, GFLAGS),
 
        /* cif */
-       COMPOSITE(0, "clk_cifout_div", mux_pll_src_cpll_gpll_npll_p, 0,
-                       RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 0, 5, DFLAGS,
+       COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
+                       RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
                        RK3399_CLKGATE_CON(10), 7, GFLAGS),
-       MUX(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
-                       RK3399_CLKSEL_CON(56), 5, 1, MFLAGS),
+
+       COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
+                        RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
 
        /* gic */
        COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,