MFTB on PPC64 should really be encoded using MFSPR.

The MFTB instruction itself is being phased out, and its functionality
is provided by MFSPR. According to the ISA docs, using MFSPR works on all known
chips except for the 601 (which did not have a timebase register anyway)
and the POWER3.

Thanks to Adhemerval Zanella for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 92a50516546ba002a2e9933ca3cc7f3a7c5050ca..5df735aaba74334883a80aafb1fea9758bb5f3aa 100644 (file)
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -266,8 +266,8 @@ def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
 }
 
 let Pattern = [(set G8RC:$rT, readcyclecounter)] in
-def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins),
-                          "mftb $rT", SprMFTB>,
+def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
+                          "mfspr $rT, 268", SprMFTB>,
             PPC970_DGroup_First, PPC970_Unit_FXU;
 
 let Defs = [X1], Uses = [X1] in

diff --git a/test/CodeGen/PowerPC/ppc64-cyclecounter.ll b/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
index c1df3c7ec2158b9e9662374fff4c461bfa8cd452..38406cabb2df5b73dfa013d4fa3a0c87ade69723 100644 (file)
--- a/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
+++ b/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
@@ -9,7 +9,7 @@ entry:
 }
 
 ; CHECK: @test1
-; CHECK: mftb
+; CHECK: mfspr 3, 268
 
 declare i64 @llvm.readcyclecounter()