Required properties:
- compatible: "rockchip,rk3288-dw-hdmi",
+ "rockchip,rk3368-dw-hdmi",
"rockchip,rk3399-dw-hdmi";
- reg: Physical base address and length of the controller's registers.
- clocks: phandle to hdmi iahb and isfr clocks.
* to enable mpll pre-divider.
*/
if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
- hdmi->dev_type == RK3399_HDMI)
+ (hdmi->dev_type == RK3399_HDMI || hdmi->dev_type == RK3368_HDMI))
hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
0x06);
else
.tmds_n_table = rockchip_werid_tmds_n_table,
};
+static const struct dw_hdmi_plat_data rk3368_hdmi_drv_data = {
+ .mode_valid = dw_hdmi_rockchip_mode_valid,
+ .mpll_cfg = rockchip_mpll_cfg,
+ .cur_ctr = rockchip_cur_ctr,
+ .phy_config = rockchip_phy_config,
+ .dev_type = RK3368_HDMI,
+};
+
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
{ .compatible = "rockchip,rk3288-dw-hdmi",
.data = &rk3288_hdmi_drv_data
},
+ {
+ .compatible = "rockchip,rk3368-dw-hdmi",
+ .data = &rk3368_hdmi_drv_data
+ },
{ .compatible = "rockchip,rk3399-dw-hdmi",
.data = &rk3399_hdmi_drv_data
},
IMX6Q_HDMI,
IMX6DL_HDMI,
RK3288_HDMI,
+ RK3368_HDMI,
RK3399_HDMI,
};
static inline bool is_rockchip(enum dw_hdmi_devtype dev_type)
{
- return dev_type == RK3288_HDMI || dev_type == RK3399_HDMI;
+ switch (dev_type) {
+ case RK3288_HDMI:
+ case RK3368_HDMI:
+ case RK3399_HDMI:
+ return true;
+ default:
+ return false;
+ }
}
void dw_hdmi_unbind(struct device *dev, struct device *master, void *data);