Add a second vector type to the VRRC register class, and fix some patterns

so that tablegen can infer all types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 4ec8fe3346d265fa1cda3820821746725fff3f22..225017cea787f250d917eb214026c1e048b12b39 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -946,11 +946,11 @@ def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
               (srl GPRC:$rS, (sub 32, GPRC:$rB))),
           (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
 
-def : Pat<(zext GPRC:$in),
+def : Pat<(i64 (zext GPRC:$in)),
           (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
-def : Pat<(anyext GPRC:$in),
+def : Pat<(i64 (anyext GPRC:$in)),
           (OR4To8 GPRC:$in, GPRC:$in)>;
-def : Pat<(trunc G8RC:$in),
+def : Pat<(i32 (trunc G8RC:$in)),
           (OR8To4 G8RC:$in, G8RC:$in)>;
 
 // SHL

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 99813fdd2d10fa29380f9bd1ae1f3d1e33769dd8..f34950054a5226a3d16d73e565a1905367082414 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -191,9 +191,9 @@ def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def VRRC : RegisterClass<"PPC", [v4f32], 128, [V0, V1, V2, V3, V4, V5, V6, V7, 
-  V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
-  V24, V25, V26, V27, V28, V29, V30, V31]>;
+def VRRC : RegisterClass<"PPC", [v4f32,v4i32], 128, [V0, V1, V2, V3, V4, V5,
+  V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
+  V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
 
 def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 
   CR3, CR4]>;