endif
#EXTRA_CFLAGS += -Dlinux -DDWC_HS_ELECT_TST
-dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o usbdev_rk30.o
+dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
+dwc_otg-objs += usbdev_rk30.o usbdev_rk2928.o
obj-$(CONFIG_DWC_OTG) := dwc_otg.o
if (!res_base)
goto fail;
- dwc_otg_device->base = ioremap(res_base->start,USBOTG_SIZE);
+ dwc_otg_device->base = ioremap(res_base->start,res_base->end-res_base->start+1);
if (dwc_otg_device->base == NULL)
{
dev_err(dev, "ioremap() failed\n");
goto fail;
dwc_otg_device->base =
- ioremap(res_base->start,USBOTG_SIZE);
+ ioremap(res_base->start,res_base->end-res_base->start+1);
DWC_PRINT("%s host2.0 reg addr: 0x%x remap:0x%x\n",__func__,
(unsigned)res_base->start, (unsigned)dwc_otg_device->base);
if (dwc_otg_device->base == NULL)
return 1;
}
-/*
- * suspend: 0 usb phy enable
- * 1 usb phy suspend
- */
-static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
-{
-#ifdef CONFIG_ARCH_RK29
- unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
-
- if(suspend) {
- *otg_phy_con1 |= (0x01<<2);
- *otg_phy_con1 |= (0x01<<3); // exit suspend.
- *otg_phy_con1 &= ~(0x01<<2);
-
- DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
- }
- else
- {
- *otg_phy_con1 |= (0x01<<2);
- *otg_phy_con1 &= ~(0x01<<3); // enter suspend.
- DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
- }
-#endif
-#ifdef CONFIG_ARCH_RK30
- unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON2);
- if(suspend) {
- *otg_phy_con1 = ((0x01<<2)<<16); // exit suspend.
- DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
- }
- else{
- *otg_phy_con1 = 0x554|(0xfff<<16); // enter suspend.
- udelay(3);
- DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
- }
-#endif
-#ifdef CONFIG_ARCH_RK2928
- unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);
- if(suspend) {
- *otg_phy_con1 = (0x01<<16); // exit suspend.
- DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
- }
- else{
- *otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend. enable dm,dp Pull-Down Resistor wlf @2012.8.10
- udelay(3);
- DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
- }
-#endif
- return suspend;
-}
-
/**
* HCD Callback structure for handling mode switching.
*/
.stop = dwc_otg_hcd_stop_cb,
.disconnect = dwc_otg_hcd_disconnect_cb,
.session_start = dwc_otg_hcd_session_start_cb,
- .suspend = dwc_otg_phy_suspend_cb,
.p = 0,//hcd
};
#endif
#ifdef CONFIG_USB20_HOST
-/*
- * suspend: 0 usb phy enable
- * 1 usb phy suspend
- */
-static int32_t host20_phy_suspend_cb( void *_p, int suspend)
-{
-#ifdef CONFIG_ARCH_RK29
- unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
- uint32_t regval;
-
- regval = *otg_phy_con1;
-
- if(suspend) {
- regval |= (0x01<<14); // exit suspend.
- regval &= ~(0x01<<13);
-
- DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
- }
- else
- {
- regval &= ~(0x01<<14); // exit suspend.
- regval |= (0x01<<13); // software control
- DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
- }
- *otg_phy_con1 = regval;
-#endif
-
-#ifdef CONFIG_ARCH_RK30
- unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON2);
- if(suspend) {
- *otg_phy_con1 = ((0x01<<2)<<16); // exit suspend.
- DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
- }
- else{
- *otg_phy_con1 = 0x554|(0xfff<<16); // enter suspend.
- udelay(3);
- DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
- }
-#endif
-#ifdef CONFIG_ARCH_RK2928
- unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON5);
- if(suspend) {
- *otg_phy_con1 = (0x01<<16); // exit suspend.
- DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
- }
- else{
- *otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend. enable dm,dp Pull-Down Resistor wlf @2012.8.10
- udelay(3);
- DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
- }
-#endif
- return suspend;
-}
static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
.start = dwc_otg_hcd_start_cb,
.stop = dwc_otg_hcd_stop_cb,
.disconnect = dwc_otg_hcd_disconnect_cb,
.session_start = dwc_otg_hcd_session_start_cb,
- .suspend = host20_phy_suspend_cb,
.p = 0,//hcd
};
DWC_PRINT("********soft connect!!!*****************************************\n");
}
}
+#if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK3066B)
+static void dwc_otg_pcd_check_vbus_timer( unsigned long pdata )
+{
+ struct device *_dev = (struct device *)pdata;
+ struct dwc_otg_platform_data *pldata = _dev->platform_data;
+ dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)_dev->platform_data));
+ dwc_otg_pcd_t * _pcd = otg_dev->pcd;
+ dwc_otg_core_if_t *core_if = GET_CORE_IF(_pcd);
+ gotgctl_data_t gctrl;
+ dctl_data_t dctl = {.d32=0};
+ //dsts_data_t gsts;
+ unsigned long flags;
+ local_irq_save(flags);
+ gctrl.d32 = dwc_read_reg32( &core_if->core_global_regs->gotgctl );
+ //gsts.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dsts);
+
+ _pcd->check_vbus_timer.expires = jiffies + (HZ); /* 1 s */
+ if( gctrl.b.bsesvld ) {
+ /* if usb not connect before ,then start connect */
+ if( _pcd->vbus_status == 0 ) {
+ dwc_otg_msc_lock(_pcd);
+ DWC_PRINT("********vbus detect*********************************************\n");
+ _pcd->vbus_status = 1;
+ /* soft disconnect */
+ dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
+ dctl.b.sftdiscon = 1;
+ dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
+ if(_pcd->conn_en)
+ {
+ schedule_delayed_work( &_pcd->reconnect , 8 ); /* delay 1 jiffies */
+ _pcd->check_vbus_timer.expires = jiffies + (HZ<<1); /* 1 s */
+ }
+
+ } else if((_pcd->conn_status>0)&&(_pcd->conn_status <3)) {
+ //dwc_otg_msc_unlock(_pcd);
+ DWC_PRINT("********soft reconnect******************************************\n");
+ //_pcd->vbus_status =0;
+
+ /* soft disconnect */
+ dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
+ dctl.b.sftdiscon = 1;
+ dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
+ /* Clear any pending interrupts */
+ dwc_write_reg32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+ if(_pcd->conn_en)
+ {
+ schedule_delayed_work( &_pcd->reconnect , 8 ); /* delay 1 jiffies */
+ _pcd->check_vbus_timer.expires = jiffies + (HZ<<1); /* 1 s */
+ }
+ }
+ else if((_pcd->conn_en)&&(_pcd->conn_status == 0))
+ {
+
+ schedule_delayed_work( &_pcd->reconnect , 8 ); /* delay 1 jiffies */
+ _pcd->check_vbus_timer.expires = jiffies + (HZ<<1); /* 1 s */
+ }
+ else if(_pcd->conn_status ==3)
+ {
+ //*????????,??????????,yk@rk,20100331*//
+ dwc_otg_msc_unlock(_pcd);
+ _pcd->conn_status++;
+ _pcd->vbus_status = 2;
+ }
+ } else {
+ //DWC_PRINT("new vbus=%d,old vbus=%d\n" , gctrl.b.bsesvld , _pcd->vbus_status );
+ _pcd->vbus_status = 0;
+ if(_pcd->conn_status)
+ {
+ _pcd->conn_status = 0;
+ dwc_otg_msc_unlock(_pcd);
+ }
+ /* every 500 ms open usb phy power and start 1 jiffies timer to get vbus */
+ if( pldata->phy_status == 0 ) {
+ /* no vbus detect here , close usb phy for 500ms */
+ pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
+ //dwc_otg20phy_suspend( 0 );
+ _pcd->check_vbus_timer.expires = jiffies + (HZ/2); /* 500 ms */
+ } else if( pldata->phy_status == 1 ) {
+ pldata->phy_suspend(pldata, USB_PHY_ENABLED);
+ // dwc_otg20phy_suspend( 1 );
+ /*20100325 yk@rk,delay 2-->8,for host connect id detect*/
+ _pcd->check_vbus_timer.expires = jiffies + 8; /* 20091127,HSL@RK,1-->2 */
+
+ }
+ }
+ //DWC_PRINT("%s:restart check vbus timer\n" , __func__ );
+ add_timer(&_pcd->check_vbus_timer);
+ local_irq_restore(flags);
+}
+#else
+
static void dwc_otg_pcd_check_vbus_timer( unsigned long data )
{
struct device *_dev = (struct device *)data;
local_irq_restore(flags);
return;
}
-
-#ifdef CONFIG_ARCH_RK30
+#endif
+#if 0 //def CONFIG_ARCH_RK30
int dwc_otg_check_dpdm(void)
{
static uint8_t * reg_base = 0;
pcd->vbus_status = 0;
pcd->phy_suspend = 0;
if(dwc_otg_is_device_mode(core_if))
- mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<4)); // delay 16 S
+ mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<2)); // delay 16 S
return 0;
}
/**
#include <linux/list.h>
#include <linux/delay.h>
#include <asm/io.h>
-#ifdef CONFIG_ARCH_RK29
-#include <mach/rk29_iomap.h>
-#include <mach/iomux.h>
-#define GRF_REG_BASE RK29_GRF_BASE
-#define USB20_OTG0_BASE RK29_USBOTG0_PHYS
-#define USB20_OTG1_BASE RK29_USBOTG1_PHYS
-#define USB11_HOST_BASE RK29_USBHOST_PHYS
-#define USBOTG_SIZE RK29_USBOTG0_SIZE
-#define USB_GRF_CON (GRF_REG_BASE+0x9C)
-#define USB_GRF_IOMUX (GRF_REG_BASE+0x68)
-#define USB_CLKGATE_CON (RK29_CRU_BASE+0x60)
-#define USB_CLKSEL_CON (RK29_CRU_BASE+0x18)
-#ifndef SCU_BASE_ADDR_VA
-#define SCU_BASE_ADDR_VA RK29_CRU_BASE
-#endif
-#define USB_IOMUX_INIT(a,b) rk29_mux_api_set(a,b)
-#endif
-
-#ifdef CONFIG_ARCH_RK30
-#include <mach/iomux.h>
-#define GRF_REG_BASE RK30_GRF_BASE
-#define USBOTG_SIZE RK30_USBOTG20_SIZE
-#define USBGRF_SOC_STATUS0 (GRF_REG_BASE+0x15c)
-#define USBGRF_UOC0_CON2 (GRF_REG_BASE+0x184)
-#define USBGRF_UOC1_CON2 (GRF_REG_BASE+0x190)
-#define USB_IOMUX_INIT(a,b) rk30_mux_api_set(a,b)
-#endif
-
-#ifdef CONFIG_ARCH_RK2928
-#include <mach/iomux.h>
-#define GRF_REG_BASE RK2928_GRF_BASE
-#define USBOTG_SIZE RK2928_USBOTG20_SIZE
-#define USBGRF_SOC_STATUS0 (GRF_REG_BASE+0x14c)
-#define USBGRF_UOC0_CON5 (GRF_REG_BASE+0x17c)
-#define USBGRF_UOC1_CON5 (GRF_REG_BASE+0x194)
-#define USB_IOMUX_INIT(a,b) rk30_mux_api_set(a,b)
-#endif
/**
* @file
*
--- /dev/null
+#ifdef CONFIG_ARCH_RK2928\r
+#endif
\ No newline at end of file
#include <linux/kernel.h>\r
#include <linux/platform_device.h>\r
#include <linux/delay.h>\r
-#ifdef CONFIG_ARCH_RK30\r
#include <linux/dma-mapping.h>\r
#include <linux/clk.h>\r
\r
#include <mach/cru.h>\r
\r
#include "usbdev_rk.h"\r
+#ifdef CONFIG_ARCH_RK30\r
\r
#define GRF_REG_BASE RK30_GRF_BASE \r
#define USBOTG_SIZE RK30_USBOTG20_SIZE\r
+#ifdef CONFIG_ARCH_RK3066B\r
+#define USBGRF_SOC_STATUS0 (GRF_REG_BASE+0xac)\r
+#define USBGRF_UOC0_CON2 (GRF_REG_BASE+0x118) // USBGRF_UOC0_CON3\r
+#define USBGRF_UOC1_CON2 (GRF_REG_BASE+0x128) // USBGRF_UOC1_CON3\r
+#else\r
#define USBGRF_SOC_STATUS0 (GRF_REG_BASE+0x15c)\r
#define USBGRF_UOC0_CON2 (GRF_REG_BASE+0x184)\r
#define USBGRF_UOC1_CON2 (GRF_REG_BASE+0x190)\r
+#endif\r
//#define USB_IOMUX_INIT(a,b) rk30_mux_api_set(a,b)\r
\r
#ifdef CONFIG_USB20_OTG\r
// usb phy config init\r
\r
// other haredware init\r
+#ifdef CONFIG_ARCH_RK3066B\r
+ rk30_mux_api_set(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME, GPIO3D_OTGDRVVBUS);\r
+#else\r
rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A_OTG_DRV_VBUS);\r
+#endif\r
}\r
void usb20otg_phy_suspend(void* pdata, int suspend)\r
{\r
// usb phy config init\r
\r
// other haredware init\r
+#ifdef CONFIG_ARCH_RK3066B\r
+ rk30_mux_api_set(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME, GPIO3D_HOSTDRVVBUS);\r
+#else\r
rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A_HOST_DRV_VBUS);\r
+#endif\r
}\r
void usb20host_phy_suspend(void* pdata, int suspend)\r
{\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff