#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/io.h>
+#include <mach/gpio.h>
+#include <mach/iomux.h>
+/*set touchscreen different type header*/
+#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI)
+#include "../../../drivers/input/touchscreen/xpt2046_ts.h"
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
+#include "../../../drivers/input/touchscreen/xpt2046_tslib_ts.h"
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
+#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
+#endif
+
+
+/*****************************************************************************************
+ * xpt2046 touch panel
+ * author: hhb@rock-chips.com
+ *****************************************************************************************/
+#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
+#define XPT2046_GPIO_INT RK30_PIN6_PB7
+#define DEBOUNCE_REPTIME 3
+
+
+static struct xpt2046_platform_data xpt2046_info = {
+ .model = 2046,
+ .keep_vref_on = 1,
+ .swap_xy = 0,
+ .debounce_max = 7,
+ .debounce_rep = DEBOUNCE_REPTIME,
+ .debounce_tol = 20,
+ .gpio_pendown = XPT2046_GPIO_INT,
+ .pendown_iomux_name = GPIO6B7_TESTCLOCKOUT_NAME,
+ .pendown_iomux_mode = GPIO6B_GPIO6B7,
+ .touch_virtualkey_length = 60,
+ .penirq_recheck_delay_usecs = 1,
+#if defined(CONFIG_TOUCHSCREEN_480X800)
+ .x_min = 0,
+ .x_max = 480,
+ .y_min = 0,
+ .y_max = 800,
+ .touch_ad_top = 3940,
+ .touch_ad_bottom = 310,
+ .touch_ad_left = 3772,
+ .touch_ad_right = 340,
+#elif defined(CONFIG_TOUCHSCREEN_800X480)
+ .x_min = 0,
+ .x_max = 800,
+ .y_min = 0,
+ .y_max = 480,
+ .touch_ad_top = 2447,
+ .touch_ad_bottom = 207,
+ .touch_ad_left = 5938,
+ .touch_ad_right = 153,
+#elif defined(CONFIG_TOUCHSCREEN_320X480)
+ .x_min = 0,
+ .x_max = 320,
+ .y_min = 0,
+ .y_max = 480,
+ .touch_ad_top = 3166,
+ .touch_ad_bottom = 256,
+ .touch_ad_left = 3658,
+ .touch_ad_right = 380,
+#endif
+};
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
+static struct xpt2046_platform_data xpt2046_info = {
+ .model = 2046,
+ .keep_vref_on = 1,
+ .swap_xy = 0,
+ .debounce_max = 7,
+ .debounce_rep = DEBOUNCE_REPTIME,
+ .debounce_tol = 20,
+ .gpio_pendown = XPT2046_GPIO_INT,
+ .pendown_iomux_name = GPIO6B7_TESTCLOCKOUT_NAME,
+ .pendown_iomux_mode = GPIO6B_GPIO6B7,
+ .touch_virtualkey_length = 60,
+ .penirq_recheck_delay_usecs = 1,
+
+#if defined(CONFIG_TOUCHSCREEN_480X800)
+ .x_min = 0,
+ .x_max = 480,
+ .y_min = 0,
+ .y_max = 800,
+ .screen_x = { 70, 410, 70, 410, 240},
+ .screen_y = { 50, 50, 740, 740, 400},
+ .uncali_x_default = { 3267, 831, 3139, 715, 1845 },
+ .uncali_y_default = { 3638, 3664, 564, 591, 2087 },
+#elif defined(CONFIG_TOUCHSCREEN_800X480)
+ .x_min = 0,
+ .x_max = 800,
+ .y_min = 0,
+ .y_max = 480,
+ .screen_x[5] = { 50, 750, 50, 750, 400};
+ .screen_y[5] = { 40, 40, 440, 440, 240};
+ .uncali_x_default[5] = { 438, 565, 3507, 3631, 2105 };
+ .uncali_y_default[5] = { 3756, 489, 3792, 534, 2159 };
+#elif defined(CONFIG_TOUCHSCREEN_320X480)
+ .x_min = 0,
+ .x_max = 320,
+ .y_min = 0,
+ .y_max = 480,
+ .screen_x[5] = { 50, 270, 50, 270, 160};
+ .screen_y[5] = { 40, 40, 440, 440, 240};
+ .uncali_x_default[5] = { 812, 3341, 851, 3371, 2183 };
+ .uncali_y_default[5] = { 442, 435, 3193, 3195, 2004 };
+#endif
+};
+#endif
+
+static struct spi_board_info board_spi_devices[] = {
+#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
+ {
+ .modalias = "xpt2046_ts",
+ .chip_select = 1,// 2,
+ .max_speed_hz = 1 * 1000 * 1000,/* (max sample rate @ 3V) * (cmd + data + overhead) */
+ .bus_num = 0,
+ .irq = XPT2046_GPIO_INT,
+ .platform_data = &xpt2046_info,
+ },
+#endif
+
+};
+
+
static struct platform_device *devices[] __initdata = {
};
static void __init machine_rk30_board_init(void)
{
rk30_i2c_register_board_info();
+ spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
#include <mach/irqs.h>
#include <mach/board.h>
#include <plat/dma-pl330.h>
-
+#include <mach/gpio.h>
+#include <mach/iomux.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource resource_dmac1[] = {
}
//end of i2c
+/*****************************************************************************************
+ * spi devices
+ * author: cmc@rock-chips.com
+ *****************************************************************************************/
+#define SPI_CHIPSELECT_NUM 2
+static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
+ {
+ .name = "spi0 cs0",
+ .cs_gpio = RK30_PIN1_PA4,
+ .cs_iomux_name = GPIO1A4_UART1SIN_SPI0CSN0_NAME,
+ .cs_iomux_mode = GPIO1A_SPI0_CSN0,
+ },
+ {
+ .name = "spi0 cs1",
+ .cs_gpio = RK30_PIN4_PB7,
+ .cs_iomux_name = GPIO4B7_SPI0CSN1_NAME,//if no iomux,set it NULL
+ .cs_iomux_mode = GPIO4B_SPI0_CSN1,
+ }
+};
+
+static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
+ {
+ .name = "spi1 cs0",
+ .cs_gpio = RK30_PIN2_PC4,
+ .cs_iomux_name = GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,
+ .cs_iomux_mode = GPIO2C_SPI1_CSN0,
+ },
+ {
+ .name = "spi1 cs1",
+ .cs_gpio = RK30_PIN2_PC7,
+ .cs_iomux_name = GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,//if no iomux,set it NULL
+ .cs_iomux_mode = GPIO2C_SPI1_CSN1,
+ }
+};
+
+static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
+{
+ int i;
+ if (cs_gpios) {
+ for (i=0; i<cs_num; i++) {
+ rk30_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
+ }
+ }
+ return 0;
+}
+
+static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
+{
+ return 0;
+}
+
+static int spi_io_fix_leakage_bug(void)
+{
+#if 0
+ gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
+#endif
+ return 0;
+}
+
+static int spi_io_resume_leakage_bug(void)
+{
+#if 0
+ gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
+#endif
+ return 0;
+}
+
+struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
+ .num_chipselect = SPI_CHIPSELECT_NUM,
+ .chipselect_gpios = rk29xx_spi0_cs_gpios,
+ .io_init = spi_io_init,
+ .io_deinit = spi_io_deinit,
+ .io_fix_leakage_bug = spi_io_fix_leakage_bug,
+ .io_resume_leakage_bug = spi_io_resume_leakage_bug,
+};
+
+struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
+ .num_chipselect = SPI_CHIPSELECT_NUM,
+ .chipselect_gpios = rk29xx_spi1_cs_gpios,
+ .io_init = spi_io_init,
+ .io_deinit = spi_io_deinit,
+ .io_fix_leakage_bug = spi_io_fix_leakage_bug,
+ .io_resume_leakage_bug = spi_io_resume_leakage_bug,
+};
+
+
+
+/*
+ * rk29xx spi master device
+ */
+#ifdef CONFIG_SPIM0_RK29
+static struct resource rk29_spi0_resources[] = {
+ {
+ .start = IRQ_SPI0,
+ .end = IRQ_SPI0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK30_SPI0_PHYS,
+ .end = RK30_SPI0_PHYS + RK30_SPI0_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DMACH_SPI0_TX,
+ .end = DMACH_SPI0_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ {
+ .start = DMACH_SPI0_RX,
+ .end = DMACH_SPI0_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device rk29xx_device_spi0m = {
+ .name = "rk29xx_spim",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(rk29_spi0_resources),
+ .resource = rk29_spi0_resources,
+ .dev = {
+ .platform_data = &rk29xx_spi0_platdata,
+ },
+};
+#endif
+
+#ifdef CONFIG_SPIM1_RK29
+static struct resource rk29_spi1_resources[] = {
+ {
+ .start = IRQ_SPI1,
+ .end = IRQ_SPI1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK30_SPI1_PHYS,
+ .end = RK30_SPI1_PHYS + RK30_SPI1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DMACH_SPI1_TX,
+ .end = DMACH_SPI1_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ {
+ .start = DMACH_SPI1_RX,
+ .end = DMACH_SPI1_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device rk29xx_device_spi1m = {
+ .name = "rk29xx_spim",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(rk29_spi1_resources),
+ .resource = rk29_spi1_resources,
+ .dev = {
+ .platform_data = &rk29xx_spi1_platdata,
+ },
+};
+#endif
+
+static void __init rk30_init_spim(void)
+{
+#ifdef CONFIG_SPIM0_RK29
+ platform_device_register(&rk29xx_device_spi0m);
+#endif
+#ifdef CONFIG_SPIM1_RK29
+ platform_device_register(&rk29xx_device_spi1m);
+#endif
+}
+
+
#ifdef CONFIG_MTD_NAND_RK29XX
static struct resource resources_nand[] = {
{
rk30_init_dma();
rk30_init_uart();
rk30_init_i2c();
+ rk30_init_spim();
#ifdef CONFIG_MTD_NAND_RK29XX
platform_device_register(&device_nand);
#endif
extern struct sys_timer rk30_timer;
+/*spi*/
+struct spi_cs_gpio {
+ const char *name;
+ unsigned int cs_gpio;
+ char *cs_iomux_name;
+ unsigned int cs_iomux_mode;
+};
+
+struct rk29xx_spi_platform_data {
+ int (*io_init)(struct spi_cs_gpio*, int);
+ int (*io_deinit)(struct spi_cs_gpio*, int);
+ int (*io_fix_leakage_bug)(void);
+ int (*io_resume_leakage_bug)(void);
+ struct spi_cs_gpio *chipselect_gpios;
+ u16 num_chipselect;
+};
+
+
#endif
const unsigned int interleave;
unsigned int flags;
};
+#define rk29_mux_api_set rk30_mux_api_set
extern int __init rk30_iomux_init(void);
extern void rk30_mux_api_set(char *name, unsigned int mode);
rk30_mux_set(&rk30_muxs[i]);
}
-#ifdef CONFIG_UART0_RK30
+#ifdef CONFIG_UART0_RK29
rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME, GPIO1A_UART0_SOUT);
rk30_mux_api_set(GPIO1A0_UART0SIN_NAME, GPIO1A_UART0_SIN);
#ifdef CONFIG_UART0_CTS_RTS_RK30
rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME, GPIO1A_UART0_CTS_N);
#endif
#endif
-#ifdef CONFIG_UART1_RK30
+#ifdef CONFIG_UART1_RK29
//UART1 OR SPIM0
rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A_UART1_SOUT);
rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A_UART1_SIN);
-#ifdef CONFIG_UART1_CTS_RTS_RK30
+#ifdef CONFIG_UART1_CTS_RTS_RK29
rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A_UART1_RTS_N);
rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A_UART1_CTS_N);
#endif
#endif
-#ifdef CONFIG_UART2_RK30
+#ifdef CONFIG_UART2_RK29
rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME, GPIO1B_UART2_SOUT);
rk30_mux_api_set(GPIO1B0_UART2SIN_NAME, GPIO1B_UART2_SIN);
#endif
-#ifdef CONFIG_UART3_RK30
+#ifdef CONFIG_UART3_RK29
rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME, GPIO3D_UART3_SOUT);
rk30_mux_api_set(GPIO3D3_UART3SIN_NAME, GPIO3D_UART3_SIN);
-#ifdef CONFIG_UART3_CTS_RTS_RK30
+#ifdef CONFIG_UART3_CTS_RTS_RK29
rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME, GPIO3D_UART3_RTS_N);
rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME, GPIO3D_UART3_CTS_N);
#endif
#endif
-#ifdef CONFIG_SPIM0_RK30
+#ifdef CONFIG_SPIM0_RK29
//UART1 OR SPIM0
rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A_SPI0_CLK);
rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A_SPI0_CSN0);
rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A_SPI0_TXD);
rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A_SPI0_RXD);
#endif
-#ifdef CONFIG_SPIM1_RK30
+#ifdef CONFIG_SPIM1_RK29
//rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME, GPIO2C_SPI1_CSN1);
rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME, GPIO2C_SPI1_RXD);
rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME, GPIO2C_SPI1_TXD);
#
config SPIM_RK29
- tristate "RK29 SPI master controller core support"
- depends on ARCH_RK29 && SPI_MASTER
+ tristate "RK SPI master controller core support"
+ depends on (ARCH_RK29 || ARCH_RK30) && SPI_MASTER
help
general driver for SPI controller core from RockChips
config SPIM0_RK29
- bool "RK29 SPI0 master controller"
+ bool "RK SPI0 master controller"
depends on SPIM_RK29
help
enable SPI0 master controller for RK29
config SPIM1_RK29
- bool "RK29 SPI1 master controller"
+ bool "RK SPI1 master controller"
depends on SPIM_RK29
help
enable SPI1 master controller for RK29
return -EBUSY;\r
}\r
DBG(KERN_INFO "dws->regs: %p\n", dws->regs);\r
- dws->irq = irq;\r
+ dws->irq = irq;\r
dws->irq_polarity = IRQF_TRIGGER_NONE;\r
dws->master = master;\r
dws->type = SSI_MOTO_SPI;\r
#ifndef __DRIVERS_SPIM_RK29XX_HEADER_H\r
#define __DRIVERS_SPIM_RK29XX_HEADER_H\r
#include <linux/io.h>\r
-#include <mach/rk29-dma-pl330.h>\r
+#ifdef CONFIG_ARCH_RK30\r
+#include <plat/dma-pl330.h>\r
+#else\r
+#include <mach/dma-pl330.h>\r
+#endif\r
\r
/* SPI register offsets */\r
#define SPIM_CTRLR0 0x0000\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff