--- /dev/null
+/dts-v1/;
+
+#include "rk3288.dtsi"
+
+/ {
+ compatible = "rockchip,rk3288-fpga";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "androidboot.console=ttyFIQ0 initrd=0x02000000,0x00800000";
+ };
+
+ fiq-debugger {
+ status = "okay";
+ };
+};
--- /dev/null
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "rockchip,rk3288";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial2 = &uart_dbg;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x500>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x501>;
+ };
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x502>;
+ };
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x503>;
+ };
+ };
+
+ gic: interrupt-controller@ffc01000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ reg = <0xffc01000 0x1000>,
+ <0xffc02000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ timer@ff810000 {
+ compatible = "rockchip,timer";
+ reg = <0xff810000 0x20>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,broadcast = <1>;
+ };
+
+ timer@ff810020 {
+ compatible = "rockchip,timer";
+ reg = <0xff810020 0x20>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,clocksource = <1>;
+ rockchip,count-up = <1>;
+ };
+
+ uart_dbg: serial@ff690000 {
+ compatible = "rockchip,serial";
+ reg = <0xff690000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ fiq-debugger {
+ compatible = "rockchip,fiq-debugger";
+ rockchip,serial-id = <2>;
+ rockchip,signal-irq = <106>;
+ rockchip,wake-irq = <0>;
+ status = "disabled";
+ };
+};
/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
+ * Copyright (C) 2013-2014 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
*
*/
+#include <../mach-rockchip/iomap.h>
#define UART_SHIFT 2
.macro addruart, rp, rv, tmp
- ldr \rp, = 0x20064000
- ldr \rv, = 0xfed64000
+ mrc p15, 0, \tmp, c0, c0, 0
+ ldr \rv, = 0x413fc090
+ cmp \tmp, \rv
+ ldreq \rp, = RK3188_UART2_PHYS
+ ldrne \rp, = RK3288_UART_DBG_PHYS
+ ldr \rv, = 0xff000000
+ mov \tmp, \rp
+ bic \tmp, \tmp, #0xff000000
+ bic \tmp, \tmp, #0x00f00000
+ add \rv, \rv, \tmp
.endm
#include "8250_32.S"
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
+ select HAVE_ARM_ARCH_TIMER
select HAVE_SMP
select LOCAL_TIMERS if SMP
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select CLKSRC_OF if OF
- help
- Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
- containing the RK2928, RK30xx and RK31xx series.
if ARCH_ROCKCHIP
help
Select a UART for debugging. -1 disable.
+config RK_FPGA
+ bool "FPGA Board"
+
endif
obj-y += common.o
obj-y += cpu.o
obj-y += rk3188.o
+obj-$(CONFIG_RK_FPGA) += fpga.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o
#define ROCKCHIP_CPU_RK3066B 0x31680000
#define ROCKCHIP_CPU_RK3188 0x31880000
#define ROCKCHIP_CPU_RK319X 0x31900000
+#define ROCKCHIP_CPU_RK3288 0x32880000
static inline bool cpu_is_rk2928(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK2928; }
static inline bool cpu_is_rk3026(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3026; }
static inline bool cpu_is_rk3066b(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3066B; }
static inline bool cpu_is_rk3188(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3188; }
static inline bool cpu_is_rk319x(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK319X; }
+static inline bool cpu_is_rk3288(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3288; }
#define ROCKCHIP_SOC_RK2926 (ROCKCHIP_CPU_RK2928 | 0x00)
#define ROCKCHIP_SOC_RK2928G (ROCKCHIP_CPU_RK2928 | 0x01)
#define ROCKCHIP_SOC_RK3188 (ROCKCHIP_CPU_RK3188 | 0x00)
#define ROCKCHIP_SOC_RK3188PLUS (ROCKCHIP_CPU_RK3188 | 0x10)
#define ROCKCHIP_SOC_RK3190 (ROCKCHIP_CPU_RK319X | 0x00)
+#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00)
static inline bool soc_is_rk2926(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2926; }
static inline bool soc_is_rk2928g(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928G; }
static inline bool soc_is_rk3188(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188; }
static inline bool soc_is_rk3188plus(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188PLUS; }
static inline bool soc_is_rk3190(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3190; }
+static inline bool soc_is_rk3288(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3288; }
#endif
--- /dev/null
+/*
+ * Device Tree support for Rockchip FPGA
+ *
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/irqchip.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include "common.h"
+#include "cpu.h"
+#include "iomap.h"
+
+static struct map_desc rk3288_io_desc[] __initdata = {
+ {
+ .virtual = (unsigned long) RK_DEBUG_UART_VIRT,
+ .pfn = __phys_to_pfn(RK3288_UART_DBG_PHYS),
+ .length = RK3288_UART_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+static void __init rk3288_fpga_map_io(void)
+{
+ iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
+ debug_ll_io_init();
+
+ rockchip_soc_id = ROCKCHIP_SOC_RK3288;
+}
+
+static void __init rk3288_fpga_init_timer(void)
+{
+ clocksource_of_init();
+}
+
+static const char * const rk3288_fpga_compat[] __initconst = {
+ "rockchip,rk3288-fpga",
+ NULL,
+};
+
+DT_MACHINE_START(RK3288_FPGA_DT, "Rockchip RK3288 FPGA (Flattened Device Tree)")
+ .map_io = rk3288_fpga_map_io,
+ .init_time = rk3288_fpga_init_timer,
+ .dt_compat = rk3288_fpga_compat,
+MACHINE_END
#ifndef __MACH_ROCKCHIP_IOMAP_H
#define __MACH_ROCKCHIP_IOMAP_H
+#ifndef __ASSEMBLY__
#include <asm/io.h>
+#endif
#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x)
#define RK3188_UART3_PHYS 0x20068000
#define RK3188_UART_SIZE SZ_4K
+#define RK3288_UART_BT_PHYS 0xff180000
+#define RK3288_UART_BB_PHYS 0xff190000
+#define RK3288_UART_DBG_PHYS 0xff690000
+#define RK3288_UART_GPS_PHYS 0xff1b0000
+#define RK3288_UART_EXP_PHYS 0xff1c0000
+#define RK3288_UART_SIZE SZ_4K
+
#endif
projects / firefly-linux-kernel-4.4.55.git / commitdiff