Remove some dead code from SPU BE that remained

from 64bit vector support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111910 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 9741672bc42d9e8135cd54b336fb5e535d382562..a00331c76359894b63199f6607152912688fc71a 100644 (file)
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -514,8 +514,6 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
     node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER";
     node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER";
     node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER";
-    node_names[(unsigned) SPUISD::HALF2VEC] = "SPUISD::HALF2VEC";
-    node_names[(unsigned) SPUISD::VEC2HALF] = "SPUISD::VEC2HALF";
   }
 
   std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
@@ -736,14 +734,12 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
   EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
   DebugLoc dl = Op.getDebugLoc();
   unsigned alignment = SN->getAlignment();
-  const bool isVec = VT.isVector();
-  EVT eltTy = isVec ? VT.getVectorElementType(): VT;
 
   switch (SN->getAddressingMode()) {
   case ISD::UNINDEXED: {
     // The vector type we really want to load from the 16-byte chunk.
     EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
-                                 eltTy, (128 / eltTy.getSizeInBits()));
+                                 VT, (128 / VT.getSizeInBits()));
 
     SDValue alignLoadVec;
     SDValue basePtr = SN->getBasePtr();
@@ -846,19 +842,11 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
       }
 #endif
 
-    SDValue insertEltOp;
-    SDValue vectorizeOp;
-    if (isVec)
-    {
-      // FIXME: this works only if the vector is 64bit!
-      insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v2i64, insertEltOffs);
-      vectorizeOp = DAG.getNode(SPUISD::HALF2VEC, dl, vecVT, theValue);
-    }
-    else
-    {
-      insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
-      vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
-    }
+    SDValue insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT,
+                                      insertEltOffs);
+    SDValue vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, 
+                                      theValue);
+
     result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
                          vectorizeOp, alignLoadVec,
                          DAG.getNode(ISD::BIT_CONVERT, dl,

diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h
index 4022679c9ec9b85d4d873f657b89ecaa4af6734e..6d3c90b7512ce0d223708c543da7b5fbcdf099a8 100644 (file)
--- a/lib/Target/CellSPU/SPUISelLowering.h
+++ b/lib/Target/CellSPU/SPUISelLowering.h
@@ -54,8 +54,6 @@ namespace llvm {
       ADD64_MARKER,             ///< i64 addition marker
       SUB64_MARKER,             ///< i64 subtraction marker
       MUL64_MARKER,             ///< i64 multiply marker
-      HALF2VEC,                 ///< Promote 64 bit vector to 128 bits
-      VEC2HALF,                 ///< Extract first 64 bits from 128 bit vector
       LAST_SPUISD               ///< Last user-defined instruction
     };
   }

diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td
index dbacfc856d4aac8ed59f5e654c138e388393513a..647da3051d3da9108d5488a3b8356c1fb397eb53 100644 (file)
--- a/lib/Target/CellSPU/SPUNodes.td
+++ b/lib/Target/CellSPU/SPUNodes.td
@@ -117,12 +117,6 @@ def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>;
 def SPU_vec_demote   : SDTypeProfile<1, 1, []>;
 def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
 
-def SPU_half_2_vec : SDTypeProfile<1, 1, []>;
-def SPUhalf2vec: SDNode<"SPUISD::HALF2VEC", SPU_half_2_vec, []>;
-
-def SPU_vec_2_half : SDTypeProfile<1, 1, []>;
-def SPUvec2half: SDNode<"SPUISD::VEC2HALF", SPU_vec_2_half, []>;
- 
 // Address high and low components, used for [r+r] type addressing
 def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
 def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;