static struct resource armadillo5x0_nor_flash_resource = {
.flags = IORESOURCE_MEM,
- .start = CS0_BASE_ADDR,
- .end = CS0_BASE_ADDR + SZ_64M - 1,
+ .start = MX31_CS0_BASE_ADDR,
+ .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
};
static struct platform_device armadillo5x0_nor_flash = {
*/
static struct resource armadillo5x0_smc911x_resources[] = {
{
- .start = CS3_BASE_ADDR,
- .end = CS3_BASE_ADDR + SZ_32M - 1,
+ .start = MX31_CS3_BASE_ADDR,
+ .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
MACHINE_START(ARMADILLO5X0, "Armadillo-500")
/* Maintainer: Alberto Panizzo */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100,
.map_io = mx31_map_io,
.init_irq = mx31_init_irq,
#include <mach/hardware.h>
#include <mach/common.h>
-#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
+#define CCM_BASE IO_ADDRESS(MX35_CCM_BASE_ADDR)
#define CCM_CCMR 0x00
#define CCM_PDR0 0x04
__raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
__raw_writel(0, CCM_BASE + CCM_CGR3);
- mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
+ mxc_timer_init(&gpt_clk, IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
return 0;
}
mx31_read_cpu_rev();
- if (mx31_revision() >= CHIP_REV_2_0) {
+ if (mx31_revision() >= MX31_CHIP_REV_2_0) {
reg = __raw_readl(MXC_CCM_PMCR1);
/* No PLL restart on DVFS switch; enable auto EMI handshake */
reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
__raw_writel(reg, MXC_CCM_PMCR1);
}
- mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
+ mxc_timer_init(&ipg_clk, IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
return 0;
}
#define CKIH_CLK_FREQ_27MHZ 27000000
#define CKIL_CLK_FREQ 32768
-#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
+#define MXC_CCM_BASE IO_ADDRESS(MX31_CCM_BASE_ADDR)
/* Register addresses */
#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
/*
* IOMUX register (base) addresses
*/
-#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
+#define IOMUX_BASE IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
#define IOMUXGPR (IOMUX_BASE + 0x008)
static struct resource kzm_smsc9118_resources[] = {
{
- .start = CS5_BASE_ADDR,
- .end = CS5_BASE_ADDR + SZ_128K - 1,
+ .start = MX31_CS5_BASE_ADDR,
+ .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
.flags = IORESOURCE_MEM,
},
{
*/
static struct map_desc kzm_io_desc[] __initdata = {
{
- .virtual = CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(CS4_BASE_ADDR),
- .length = CS4_SIZE,
+ .virtual = MX31_CS4_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
+ .length = MX31_CS4_SIZE,
.type = MT_DEVICE
},
{
- .virtual = CS5_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(CS5_BASE_ADDR),
- .length = CS5_SIZE,
+ .virtual = MX31_CS5_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
+ .length = MX31_CS5_SIZE,
.type = MT_DEVICE
},
};
* initialize __mach_desc_KZM_ARM11_01 data structure.
*/
MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = kzm_map_io,
.init_irq = mx31_init_irq,
static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
- .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
+ .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
.irq = EXPIO_INT_XUART_INTA,
.uartclk = 14745600,
.regshift = 0,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
}, {
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
- .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
+ .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
.irq = EXPIO_INT_XUART_INTB,
.uartclk = 14745600,
.regshift = 0,
*/
static struct map_desc mx31ads_io_desc[] __initdata = {
{
- .virtual = CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(CS4_BASE_ADDR),
- .length = CS4_SIZE / 2,
+ .virtual = MX31_CS4_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
+ .length = MX31_CS4_SIZE / 2,
.type = MT_DEVICE
},
};
*/
MACHINE_START(MX31ADS, "Freescale MX31ADS")
/* Maintainer: Freescale Semiconductor, Inc. */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31ads_map_io,
.init_irq = mx31ads_init_irq,
static struct resource smsc91x_resources[] = {
{
- .start = CS4_BASE_ADDR,
- .end = CS4_BASE_ADDR + 0xffff,
+ .start = MX31_CS4_BASE_ADDR,
+ .end = MX31_CS4_BASE_ADDR + 0xffff,
.flags = IORESOURCE_MEM,
},
{
};
MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io,
.init_irq = mx31_init_irq,
static struct resource smsc911x_resources[] = {
{
- .start = CS4_BASE_ADDR,
- .end = CS4_BASE_ADDR + 0x100,
+ .start = MX31_CS4_BASE_ADDR,
+ .end = MX31_CS4_BASE_ADDR + 0x100,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
*/
static struct map_desc mx31lite_io_desc[] __initdata = {
{
- .virtual = CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(CS4_BASE_ADDR),
- .length = CS4_SIZE,
+ .virtual = MX31_CS4_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
+ .length = MX31_CS4_SIZE,
.type = MT_DEVICE
}
};
MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
/* Maintainer: Freescale Semiconductor, Inc. */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31lite_map_io,
.init_irq = mx31_init_irq,
MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
/* Maintainer: Valentin Longchamp, EPFL Mobots group */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io,
.init_irq = mx31_init_irq,
*/
static struct map_desc mx31pdk_io_desc[] __initdata = {
{
- .virtual = CS5_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(CS5_BASE_ADDR),
- .length = CS5_SIZE,
+ .virtual = MX31_CS5_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
+ .length = MX31_CS5_SIZE,
.type = MT_DEVICE,
},
};
*/
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
/* Maintainer: Freescale Semiconductor, Inc. */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31pdk_map_io,
.init_irq = mx31_init_irq,
MACHINE_START(MX35_3DS, "Freescale MX35PDK")
/* Maintainer: Freescale Semiconductor, Inc */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX35_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx35_map_io,
.init_irq = mx35_init_irq,
static struct resource smsc911x_resources[] = {
{
- .start = CS1_BASE_ADDR + 0x300,
- .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
+ .start = MX31_CS1_BASE_ADDR + 0x300,
+ .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
};
static struct resource pcm038_sram_resource = {
- .start = CS4_BASE_ADDR,
- .end = CS4_BASE_ADDR + 512 * 1024 - 1,
+ .start = MX31_CS4_BASE_ADDR,
+ .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
.flags = IORESOURCE_MEM,
};
static struct resource pcm970_sja1000_resources[] = {
{
- .start = CS5_BASE_ADDR,
- .end = CS5_BASE_ADDR + 0x100 - 1,
+ .start = MX31_CS5_BASE_ADDR,
+ .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
MACHINE_START(PCM037, "Phytec Phycore pcm037")
/* Maintainer: Pengutronix */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io,
.init_irq = mx31_init_irq,
MACHINE_START(PCM043, "Phytec Phycore pcm043")
/* Maintainer: Pengutronix */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX35_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx35_map_io,
.init_irq = mx35_init_irq,
#define QONG_FPGA_VERSION(major, minor, rev) \
(((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
-#define QONG_FPGA_BASEADDR CS1_BASE_ADDR
+#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
};
static struct resource qong_flash_resource = {
- .start = CS0_BASE_ADDR,
- .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
+ .start = MX31_CS0_BASE_ADDR,
+ .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
.flags = IORESOURCE_MEM,
};
};
static struct resource qong_nand_resource = {
- .start = CS3_BASE_ADDR,
- .end = CS3_BASE_ADDR + SZ_32M - 1,
+ .start = MX31_CS3_BASE_ADDR,
+ .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
/* Maintainer: DENX Software Engineering GmbH */
- .phys_io = AIPS1_BASE_ADDR,
- .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .phys_io = MX31_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io,
.init_irq = mx31_init_irq,
/*
* KZM-ARM11-01 Board Control Registers on FPGA
*/
-#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000)
-#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001)
-#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002)
-#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004)
-#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008)
-#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010)
-#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020)
-#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003)
+#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
+#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
+#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
+#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
+#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
+#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
+#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
+#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
/*
* External UART for touch panel on FPGA
*/
-#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050)
+#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */