return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
N->getOperand(0), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32));
- case ARMISD::RBIT: {
- EVT VT = N->getValueType(0);
- SDValue Ops[] = { N->getOperand(0),
- getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getMachineNode(ARM::RBIT, dl, VT, Ops, 3);
- }
case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only())
break;
def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
[SDNPHasChain]>;
+def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
+
//===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions.
//
}
def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "rbit", "\t$dst, $src", []>, Requires<[IsARM, HasV6T2]> {
+ "rbit", "\t$dst, $src",
+ [(set GPR:$dst, (ARMrbit GPR:$src))]>,
+ Requires<[IsARM, HasV6T2]> {
let Inst{7-4} = 0b0011;
let Inst{11-8} = 0b1111;
let Inst{19-16} = 0b1111;
"clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "rbit", "\t$dst, $src", []>;
+ "rbit", "\t$dst, $src",
+ [(set GPR:$dst, (ARMrbit GPR:$src))]>;
def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;