+++ /dev/null
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-#include "skeleton.dtsi"
-#include "rk3036-clocks.dtsi"
-#include "rk3036-pinctrl.dtsi"
-#include <dt-bindings/suspend/rockchip-pm.h>
-
-/ {
- compatible = "rockchip,rk3036";
- rockchip,sram = <&sram>;
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- lcdc = &lcdc;
- spi0 = &spi0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf01>;
- };
- };
-
- gic: interrupt-controller@10139000 {
- compatible = "arm,cortex-a15-gic";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- reg = <0x10139000 0x1000>,
- <0x1013a000 0x1000>;
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cpu_axi_bus: cpu_axi_bus {
- compatible = "rockchip,cpu_axi_bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- qos {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- core {
- reg = <0x1012a000 0x20>;
- rockchip,priority = <3 2>;
- };
- peri {
- reg = <0x1012c000 0x20>;
- };
- gpu {
- reg = <0x1012d000 0x20>;
- };
- vpu {
- reg = <0x1012e000 0x20>;
- };
- hevc {
- reg = <0x1012e080 0x20>;
- };
- vio {
- reg = <0x1012f000 0x20>;
- rockchip,priority = <3 3>;
- };
- };
-
- msch {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- msch@10128000 {
- reg = <0x10128000 0x40>;
- rockchip,read-latency = <0x80>;
- };
- };
- };
-
- sram: sram@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0x2000>;
- map-exec;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
- };
-
- timer@20044000 {
- compatible = "rockchip,timer";
- reg = <0x20044000 0x20>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,broadcast = <1>;
- };
-
- watchdog: wdt@2004c000 {
- compatible = "rockchip,watch dog";
- reg = <0x2004c000 0x100>;
- clocks = <&clk_gates7 15>;
- clock-names = "pclk_wdt";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,irq = <1>;
- rockchip,timeout = <60>;
- rockchip,atboot = <1>;
- rockchip,debug = <0>;
- status = "disabled";
- };
-
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,amba-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- pdma: pdma@20078000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x20078000 0x4000>;
- clocks = <&clk_gates5 1>;
- clock-names = "apb_pclk";
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- };
- };
-
- reset: reset@20000110{
- compatible = "rockchip,reset";
- reg = <0x20000110 0x24>;
- rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
- #reset-cells = <1>;
- };
-
- nandc: nandc@10500000 {
- compatible = "rockchip,rk-nandc";
- reg = <0x10500000 0x4000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- //pinctrl-names = "default";
- //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
- nandc_id = <0>;
- clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
- clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
- };
-
- nandc0reg: nandc0@10500000 {
- compatible = "rockchip,rk-nandc";
- reg = <0x10500000 0x4000>;
- };
-
- spi0: spi@20074000 {
- compatible = "rockchip,rockchip-spi";
- reg = <0x20074000 0x1000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
- rockchip,spi-src-clk = <0>;
- num-cs = <2>;
- clocks =<&clk_spi0>, <&clk_gates2 9>;
- clock-names = "spi","pclk_spi0";
- dmas = <&pdma 8>, <&pdma 9>;
- #dma-cells = <2>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- uart0: serial@20060000 {
- compatible = "rockchip,serial";
- reg = <0x20060000 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&clk_uart0>, <&clk_gates8 0>;
- clock-names = "sclk_uart", "pclk_uart";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&pdma 2>, <&pdma 3>;
- #dma-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "disabled";
- };
-
- uart1: serial@20064000 {
- compatible = "rockchip,serial";
- reg = <0x20064000 0x100>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&clk_uart1>, <&clk_gates8 1>;
- clock-names = "sclk_uart", "pclk_uart";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&pdma 4>, <&pdma 5>;
- #dma-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer>;
- status = "disabled";
- };
-
- uart2: serial@20068000 {
- compatible = "rockchip,serial";
- reg = <0x20068000 0x100>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&clk_uart2>, <&clk_gates8 2>;
- clock-names = "sclk_uart", "pclk_uart";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&pdma 6>, <&pdma 7>;
- #dma-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
- status = "disabled";
- };
-
- fiq-debugger {
- compatible = "rockchip,fiq-debugger";
- rockchip,serial-id = <2>;
- rockchip,signal-irq = <106>;
- rockchip,wake-irq = <0>;
- status = "disabled";
- };
-
- clocks-init{
- compatible = "rockchip,clocks-init";
- rockchip,clocks-init-parent =
- <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
- <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
- <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
- <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
- <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
- rockchip,clocks-init-rate =
- <&clk_core 1200000000>, <&clk_gpll 1188000000>,
- <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
- <&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
- <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
- <&clk_gpu 400000000>, <&aclk_vio_pre 300000000>,
- <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
- <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
- <&clk_mac_ref_div 25000000>;
- /* rockchip,clocks-uboot-has-init =
- <&aclk_vio1>;*/
- };
-
- clocks-enable {
- compatible = "rockchip,clocks-enable";
- clocks =
- /*PD_CORE*/
- <&clk_gates0 0>, <&clk_gates0 7>,
-
- /*PD_CPU*/
- <&clk_gates0 3>, <&clk_gates0 4>,
- <&clk_gates0 5>,
-
- /*TIMER*/
- <&clk_gates1 0>, <&clk_gates1 1>,
- <&clk_gates2 4>, <&clk_gates2 5>,
-
- /*PD_PERI*/
- <&clk_gates2 0>, <&hclk_peri_pre>,
- <&pclk_peri_pre>, <&clk_gates2 1>,
-
- /*aclk_cpu_pre*/
- <&clk_gates4 12>,/*aclk_intmem*/
- <&clk_gates4 10>,/*aclk_strc_sys*/
-
- /*hclk_cpu_pre*/
- <&clk_gates5 6>,/*hclk_rom*/
-
- /*pclk_cpu_pre*/
- <&clk_gates5 4>,/*pclk_grf*/
- <&clk_gates5 7>,/*pclk_ddrupctl*/
- <&clk_gates5 14>,/*pclk_acodec*/
- <&clk_gates3 8>,/*pclk_hdmi*/
-
- /*aclk_peri_pre*/
- <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
- //<&clk_gates5 1>,/*aclk_dmac2*/
- <&clk_gates9 15>,/*aclk_peri_niu*/
- <&clk_gates4 2>,/*aclk_cpu_peri*/
-
- /*hclk_peri_pre*/
- <&clk_gates4 0>,/*hclk_peri_matrix*/
- <&clk_gates9 13>,/*hclk_usb_peri*/
- <&clk_gates9 14>,/*hclk_peri_arbi*/
-
- /*pclk_peri_pre*/
- <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
-
- /*hclk_vio_pre*/
- <&clk_gates6 12>,/*hclk_vio_bus*/
- <&clk_gates9 5>,/*hclk_lcdc*/
-
- /*aclk_vio_pre*/
- <&clk_gates6 13>,/*aclk_vio*/
- <&clk_gates9 6>,/*aclk_lcdc*/
-
- /*UART*/
- <&clk_gates1 12>,
- <&clk_gates1 13>,
- <&clk_gates8 2>,/*pclk_uart2*/
-
- <&clk_gpu>,
-
- /*jtag*/
- <&clk_gates1 3>;/*clk_jtag*/
- };
-
- i2c0: i2c@20072000 {
- compatible = "rockchip,rk30-i2c";
- reg = <0x20072000 0x1000>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c0_sda &i2c0_scl>;
- pinctrl-1 = <&i2c0_gpio>;
- gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates8 4>;
- rockchip,check-idle = <1>;
- status = "disabled";
- };
-
- i2c1: i2c@20056000 {
- compatible = "rockchip,rk30-i2c";
- reg = <0x20056000 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c1_sda &i2c1_scl>;
- pinctrl-1 = <&i2c1_gpio>;
- gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates8 5>;
- rockchip,check-idle = <1>;
- status = "disabled";
- };
-
- i2c2: i2c@2005a000 {
- compatible = "rockchip,rk30-i2c";
- reg = <0x2005a000 0x1000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c2_sda &i2c2_scl>;
- pinctrl-1 = <&i2c2_gpio>;
- gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates8 6>;
- rockchip,check-idle = <1>;
- status = "disabled";
- };
-
- i2s: i2s@10220000 {
- compatible = "rockchip-i2s";
- reg = <0x10220000 0x1000>;
- i2s-id = <0>;
- clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
- clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&pdma 0>, <&pdma 1>;
- //#dma-cells = <2>;
- dma-names = "tx", "rx";
- //pinctrl-names = "default", "sleep";
- //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
- //pinctrl-1 = <&i2s_gpio>;
- };
-
- codec: codec@20030000 {
- compatible = "rk3036-codec";
- reg = <0x20030000 0x1000>;
- spk_ctl_io = <&gpio1 GPIO_A0 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_gpio>;
-
- boot_depop = <1>;
- pa_enable_time = <1000>;
- clocks = <&clk_gates5 14>;
- clock-names = "g_pclk_acodec";
- };
-
- spdif: spdif@10204000 {
- compatible = "rockchip-spdif";
- reg = <0x10204000 0x1000>;
- clocks = <&clk_spdif>;
- clock-names = "spdif_mclk";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&pdma 13>;
- //#dma-cells = <1>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdif_tx>;
- };
-
- pwm0: pwm@20050000 {
- compatible = "rockchip,rk-pwm";
- reg = <0x20050000 0x10>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
- status = "disabled";
- };
-
- pwm1: pwm@20050010 {
- compatible = "rockchip,rk-pwm";
- reg = <0x20050010 0x10>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
- status = "disabled";
- };
-
- pwm2: pwm@20050020 {
- compatible = "rockchip,rk-pwm";
- reg = <0x20050020 0x10>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
- status = "disabled";
- };
-
- pwm3: pwm@20050030 {
- compatible = "rockchip,rk-pwm";
- reg = <0x20050030 0x10>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
- status = "disabled";
- };
-
- remotectl: pwm@20050030 {
- compatible = "rockchip,remotectl-pwm";
- reg = <0x20050030 0x10>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
- remote_pwm_id = <3>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
- };
-
- emmc: rksdmmc@1021c000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
- reg = <0x1021c000 0x4000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- //pinctrl-names = "default",,"suspend";
- //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
- clocks = <&clk_emmc>, <&clk_gates7 0>;
- clock-names = "clk_mmc", "hclk_mmc";
- dmas = <&pdma 12>;
- dma-names = "dw_mci";
- num-slots = <1>;
- fifo-depth = <0x100>;
- bus-width = <8>;
- };
-
-
- sdmmc: rksdmmc@10214000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
- reg = <0x10214000 0x4000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "idle", "udbg";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
- pinctrl-1 = <&sdmmc0_gpio>;
- pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
- cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
- clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
- clock-names = "clk_mmc", "hclk_mmc";
- dmas = <&pdma 10>;
- dma-names = "dw_mci";
- num-slots = <1>;
- fifo-depth = <0x100>;
- bus-width = <4>;
- };
-
- sdio: rksdmmc@10218000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
- reg = <0x10218000 0x4000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default","idle";
- pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
- pinctrl-1 = <&sdio0_gpio>;
- clocks = <&clk_sdio>, <&clk_gates5 11>;
- clock-names = "clk_mmc", "hclk_mmc";
- dmas = <&pdma 11>;
- dma-names = "dw_mci";
- num-slots = <1>;
- fifo-depth = <0x100>;
- bus-width = <4>;
- };
- gpu {
- compatible = "arm,mali400";
- reg = <0x10091000 0x200>,
- <0x10090000 0x100>,
- <0x10093000 0x100>,
- <0x10098000 0x1100>,
- <0x10094000 0x100>;
- reg-names = "Mali_L2",
- "Mali_GP",
- "Mali_GP_MMU",
- "Mali_PP0",
- "Mali_PP0_MMU";
-
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "Mali_GP_IRQ",
- "Mali_GP_MMU_IRQ",
- "Mali_PP0_IRQ",
- "Mali_PP0_MMU_IRQ";
- };
- dwc_control_usb: dwc-control-usb@20008000 {
- compatible = "rockchip,rk3036-dwc-control-usb";
- reg = <0x20008000 0x4>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg_bvalid",
- "otg0_linestate",
- "otg1_linestate";
- clocks = <&clk_gates9 13>;
- clock-names = "hclk_usb_peri";
- rockchip,remote_wakeup;
- rockchip,usb_irq_wakeup;
- resets = <&reset RK3036_RST_USBPOR>;
- reset-names = "usbphy_por";
- usb_bc{
- compatible = "rockchip,ctrl";
- rk_usb,bvalid = <0x14c 8 1>;
- rk_usb,iddig = <0x14c 11 1>;
- rk_usb,line = <0x14c 9 2>;
- rk_usb,softctrl = <0x17c 0 1>;
- rk_usb,opmode = <0x17c 2 2>;
- rk_usb,xcvrsel = <0x17c 4 2>;
- rk_usb,termsel = <0x17c 6 1>;
- };
- };
- usb0: usb@10180000 {
- compatible = "rockchip,rk3036_usb20_otg";
- reg = <0x10180000 0x40000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates1 5>, <&clk_gates5 13>;
- clock-names = "clk_usbphy0", "hclk_usb0";
- resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
- <&reset RK3036_RST_OTGC0>;
- reset-names = "otg_ahb", "otg_phy", "otg_controller";
- /*0 - Normal, 1 - Force Host, 2 - Force Device*/
- rockchip,usb-mode = <0>;
- };
-
- usb1: usb@101c0000 {
- compatible = "rockchip,rk3036_usb20_host";
- reg = <0x101c0000 0x40000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates1 6>, <&clk_gates7 3>;
- clock-names = "clk_usbphy1", "hclk_usb1";
- resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
- <&reset RK3036_RST_OTGC1>;
- reset-names = "host_ahb", "host_phy", "host_controller";
- };
-
- fb: fb{
- compatible = "rockchip,rk-fb";
- rockchip,disp-mode = <NO_DUAL>;
- rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
- };
-
- rk_screen: rk_screen{
- compatible = "rockchip,screen";
- };
-
- lcdc: lcdc@10118000 {
- compatible = "rockchip,rk3036-lcdc";
- reg = <0x10118000 0x1000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
- rockchip,iommu-enabled = <1>;
- };
-
- hdmi: hdmi@20034000 {
- compatible = "rockchip,rk3036-hdmi";
- reg = <0x20034000 0x4000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,hdmi_lcdc_source = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
- pinctrl-1 = <&hdmi_gpio>;
- clocks = <&clk_gates3 8>;
- clock-names = "pclk_hdmi";
- status = "disabled";
- };
-
- tve: tve{
- compatible = "rockchip,rk3036-tve";
- reg = <0x10118200 0x100>;
- saturation = <0x00386346>;
- brightcontrast = <0x00008b00>;
- adjtiming = <0xa6c00880>;
- lumafilter0 = <0x02ff0000>;
- lumafilter1 = <0xf40202fd>;
- lumafilter2 = <0xf332d919>;
- daclevel = <0x3e>;
- status = "disabled";
- };
-
- ion {
- compatible = "rockchip,ion";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
- compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <4>;
- reg = <0x00000000 0x00000000>; /* 0MB */
- };
- rockchip,ion-heap@0 { /* VMALLOC HEAP */
- compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <0>;
- };
- };
-
- /*vpu: vpu_service@10108000 {
- compatible = "vpu_service";
- iommu_enabled = <1>;
- reg = <0x10108000 0x800>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- name = "vpu_service";
- status = "okay";
- };
-
- hevc: hevc_service@1010c000 {
- compatible = "rockchip,hevc_service";
- iommu_enabled = <1>;
- reg = <0x1010c000 0x400>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
- name = "hevc_service";
- status = "okay";
- };*/
- vpu: vpu_service {
- compatible = "rockchip,vpu_sub";
- iommu_enabled = <1>;
- reg = <0x10108400 0x400>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- dev_mode = <0>;
- name = "vpu_service";
- };
-
- hevc: hevc_service {
- compatible = "rockchip,hevc_sub";
- iommu_enabled = <1>;
- reg = <0x1010c000 0x400>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- dev_mode = <1>;
- name = "hevc_service";
- };
-
- vpu_combo: vpu_combo@ff9a0000 {
- compatible = "rockchip,vpu_combo";
- subcnt = <2>;
- rockchip,sub = <&vpu>, <&hevc>;
- clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
- mode_bit = <3>;
- mode_ctrl = <0x144>;
- name = "vpu_combo";
- status = "okay";
- };
-
- vop_mmu {
- dbgname = "vop";
- compatible = "rockchip,vop_mmu";
- reg = <0x10118300 0x100>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
- };
-
- hevc_mmu {
- dbgname = "hevc";
- compatible = "rockchip,hevc_mmu";
- reg = <0x1010c440 0x40>,
- <0x1010c480 0x40>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hevc_mmu";
- };
-
- vpu_mmu {
- dbgname = "vpu";
- compatible = "rockchip,vpu_mmu";
- reg = <0x10108800 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
- };
-
- rockchip_suspend: rockchip_suspend {
- rockchip,ctrbits = <
- (0
- //|RKPM_CTR_PWR_DMNS
- |RKPM_CTR_GTCLKS
- |RKPM_CTR_PLLS
- |RKPM_CTR_IDLESRAM_MD
- |RKPM_CTR_DDR
- |RKPM_CTR_VOLTS
- |RKPM_CTR_VOL_PWM2
-
- //|RKPM_CTR_GPIOS
- //|RKPM_CTR_SYSCLK_DIV
- //|RKPM_CTR_IDLEAUTO_MD
- //|RKPM_CTR_ARMOFF_LPMD
- //|RKPM_CTR_ARMOFF_LOGDP_LPMD
- )
- >;
-/*
- rockchip,pmic-suspend_gpios = <
- RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
- >;
- rockchip,pmic-resume_gpios = <
- RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
- >;
-*/
- };
-
- vmac: eth@10200000 {
- compatible = "rockchip,vmac";
- reg = <0x10200000 0x4000>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clk_mac_pll>, <&clk_mac_ref>,
- <&clk_mac_pll_div>, <&clk_mac_ref_div>,
- <&clk_gates2 6>, <&clk_gates3 5>;
- clock-names = "clk_mac_pll", "clk_mac_ref",
- "clk_mac_pll_div", "clk_mac_ref_div",
- "clk_tx_rx_gate", "hclk_mac";
- pinctrl-names = "default";
- pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;
- };
-};
projects / firefly-linux-kernel-4.4.55.git / commitdiff