One more spot where the new arm mode LDR instruction representation

doesn't need the additional addrmode2 register operand. Missed it the first
time around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 85a0981ec6c7ccc471a22126d86d50c582049f58..3715ec002c56addfc95f5de1ec5a6b73b23df721 100644 (file)
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -860,7 +860,9 @@ static void InsertLDR_STR(MachineBasicBlock &MBB,
                           ARMCC::CondCodes Pred, unsigned PredReg,
                           const TargetInstrInfo *TII, bool isT2) {
   int Offset = OffImm;
-  if (!isT2) {
+  // FIXME: This fancy offset encoding stuff goes away when we're done
+  // removing addrmode2.
+  if (!isT2 && !isDef) {
     if (OffImm < 0)
       Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
     else
@@ -871,8 +873,6 @@ static void InsertLDR_STR(MachineBasicBlock &MBB,
                                       TII->get(NewOpc))
       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
-    if (!isT2)
-      MIB.addReg(OffReg,  getKillRegState(OffKill)|getUndefRegState(OffUndef));
     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
   } else {
     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),